Message ID | 20240919-pcie_ep_range-v1-8-b3e9d62780b7@nxp.com (mailing list archive) |
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State | New, archived |
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charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240919-pcie_ep_range-v1-8-b3e9d62780b7@nxp.com> References: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com> In-Reply-To: <20240919-pcie_ep_range-v1-0-b3e9d62780b7@nxp.com> To: Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= <kw@linux.com>, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Abraham I <kishon@kernel.org>, Saravana Kannan <saravanak@google.com>, Jingoo Han <jingoohan1@gmail.com>, Gustavo Pimentel <gustavo.pimentel@synopsys.com>, Jesper Nilsson <jesper.nilsson@axis.com>, Richard Zhu <hongxing.zhu@nxp.com>, Lucas Stach <l.stach@pengutronix.de>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com> Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, =?utf-8?q?Krzys?= =?utf-8?q?ztof_Wilczy=C5=84ski?= <kwilczynski@kernel.org>, Frank Li <Frank.Li@nxp.com> X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; 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PCI-EP: Add 'ranges' support for PCI endpoint devices
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diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 808d1f1054173..bdc2b372e6c13 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -961,7 +961,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) goto err_clk_disable; } - ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, + imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ? + PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC); if (ret) { dev_err(dev, "unable to set PCIe PHY mode\n"); goto err_phy_exit;
Fix hardcoding to Root Complex (RC) mode by adding a drvdata mode check. Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode. Fixes: 8026f2d8e8a9 ("PCI: imx6: Call common PHY API to set mode, speed, and submode") Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)