From patchwork Thu Sep 19 07:47:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gowthami Thiagarajan X-Patchwork-Id: 13807464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8AAFECE8D5D for ; Thu, 19 Sep 2024 07:53:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qXqZhA025IHL2HVMPEpBFcxBfY6x7g+sY9PLbhMupHg=; b=fmN/SzfAaeFc6iZ+lvqzzNVcwR 3Oc5QXmBDpvAE5FZakX4T7MWwynk3Yn+Vd5RWaxPX33LKYvovhOmy9nhi69abYWVaeKhpOgc0OODc X0oGaY2hDY95yl/6QnGOtiBwqY5tUtI6IQzYSeXtKomEOOuqv9osPjAjqAkRpUZktzdYFaW9ipnoH J8IIUm9gKO0IGksFZ1xvs60K++tkrwxVNK48V28tfFseT88+oOmWkFb0ktmJphGeuHpUiuVhd0wl+ Y5aait6OCJ8chWSR10b5+hOaHQBy3yspCSnVHxgyuO9ZfrAFl2/vDi3pDttKNkU7bpaptlcDAw77i yJ/E4tlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1srByp-00000009iYm-3rer; Thu, 19 Sep 2024 07:53:35 +0000 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174] helo=mx0b-0016f401.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1srBtg-00000009h8B-1oxL for linux-arm-kernel@lists.infradead.org; Thu, 19 Sep 2024 07:48:22 +0000 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48J6KVN3031226; Thu, 19 Sep 2024 00:47:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=q XqZhA025IHL2HVMPEpBFcxBfY6x7g+sY9PLbhMupHg=; b=Vgu6X2jbcDKPO9LKG SDASrEdD5CSc2pCv2Tw99LtctVV3Zd4fqoDxtfhrJaVHEDgdvtaSq0NhbCmwUutG pclhcIxCGUizO6EBQCiwkE3y6LeVkms7tOIIXHsvG/ZW6s0cUmN26NNUj40bvXde O6hMkHChfiVsoBFpcgJ/WtHeonG9xpN7Bk9SiBeudgJhMgxJwI29qurFqOH18a6z IRqG5cBPmqnXztO0qA12xlP43ZOqco+bxmQZiv6tOwzElc2e0TBk0MbXfdz/W+uD tzy1kEAocfXWIKFZy6Fk3kb1sKEEpN7GrTMWDrwqk18TkPcTv9i1skCHUCK2xFyF ZQe/A== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41qdwgg7um-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Sep 2024 00:47:42 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 19 Sep 2024 00:47:34 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 19 Sep 2024 00:47:34 -0700 Received: from IPBU-BLR-SERVER1.marvell.com (IPBU-BLR-SERVER1.marvell.com [10.28.8.41]) by maili.marvell.com (Postfix) with ESMTP id 0CD133F7082; Thu, 19 Sep 2024 00:47:31 -0700 (PDT) From: Gowthami Thiagarajan To: , , , CC: , , , Gowthami Thiagarajan Subject: [PATCH v8 3/6] perf/marvell: Refactor to add version - no functional change Date: Thu, 19 Sep 2024 13:17:14 +0530 Message-ID: <20240919074717.3276854-4-gthiagarajan@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240919074717.3276854-1-gthiagarajan@marvell.com> References: <20240919074717.3276854-1-gthiagarajan@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: j3sEfGz4t-otLrDzBAgS8uRF4eQp5anT X-Proofpoint-ORIG-GUID: j3sEfGz4t-otLrDzBAgS8uRF4eQp5anT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_004820_932005_96736034 X-CRM114-Status: GOOD ( 18.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This change is aimed at improving the maintainability of the code and laying the groundwork for versioning within the driver. No functional changes are introduced in this commit; the driver's behavior and performance remain unchanged. Signed-off-by: Gowthami Thiagarajan --- drivers/perf/marvell_cn10k_ddr_pmu.c | 63 ++++++++++++++++++---------- 1 file changed, 42 insertions(+), 21 deletions(-) diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn10k_ddr_pmu.c index 648ad3a740bf..65422fd5ddd2 100644 --- a/drivers/perf/marvell_cn10k_ddr_pmu.c +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c @@ -124,10 +124,19 @@ #define CN10K_DDRC_PERF_CNT_VALUE_WR_OP 0x80D0 #define CN10K_DDRC_PERF_CNT_VALUE_RD_OP 0x80D8 +enum mrvl_ddr_pmu_version { + DDR_PMU_V1 = 1, +}; + +struct ddr_pmu_data { + int id; +}; + struct cn10k_ddr_pmu { struct pmu pmu; void __iomem *base; const struct ddr_pmu_platform_data *p_data; + int version; unsigned int cpu; struct device *dev; int active_events; @@ -738,12 +747,19 @@ static const struct ddr_pmu_platform_data cn10k_ddr_pmu_pdata = { .ops = &ddr_pmu_ops, }; +#if defined(CONFIG_ACPI) || defined(CONFIG_OF) +static const struct ddr_pmu_data ddr_pmu_data = { + .id = DDR_PMU_V1, +}; +#endif + static int cn10k_ddr_perf_probe(struct platform_device *pdev) { const struct ddr_pmu_data *dev_data; struct cn10k_ddr_pmu *ddr_pmu; struct resource *res; void __iomem *base; + int version; char *name; int ret; @@ -760,31 +776,36 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev) return -ENODEV; } + version = dev_data->id; + ddr_pmu->version = version; + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); ddr_pmu->base = base; - ddr_pmu->p_data = &cn10k_ddr_pmu_pdata; - /* Setup the PMU counter to work in manual mode */ - writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base + - ddr_pmu->p_data->ddrc_perf_cnt_op_mode_ctrl); - - ddr_pmu->pmu = (struct pmu) { - .module = THIS_MODULE, - .capabilities = PERF_PMU_CAP_NO_EXCLUDE, - .task_ctx_nr = perf_invalid_context, - .attr_groups = cn10k_attr_groups, - .event_init = cn10k_ddr_perf_event_init, - .add = cn10k_ddr_perf_event_add, - .del = cn10k_ddr_perf_event_del, - .start = cn10k_ddr_perf_event_start, - .stop = cn10k_ddr_perf_event_stop, - .read = cn10k_ddr_perf_event_update, - .pmu_enable = cn10k_ddr_perf_pmu_enable, - .pmu_disable = cn10k_ddr_perf_pmu_disable, - }; + if (version == DDR_PMU_V1) { + ddr_pmu->p_data = &cn10k_ddr_pmu_pdata; + /* Setup the PMU counter to work in manual mode */ + writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base + + ddr_pmu->p_data->ddrc_perf_cnt_op_mode_ctrl); + + ddr_pmu->pmu = (struct pmu) { + .module = THIS_MODULE, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, + .task_ctx_nr = perf_invalid_context, + .attr_groups = cn10k_attr_groups, + .event_init = cn10k_ddr_perf_event_init, + .add = cn10k_ddr_perf_event_add, + .del = cn10k_ddr_perf_event_del, + .start = cn10k_ddr_perf_event_start, + .stop = cn10k_ddr_perf_event_stop, + .read = cn10k_ddr_perf_event_update, + .pmu_enable = cn10k_ddr_perf_pmu_enable, + .pmu_disable = cn10k_ddr_perf_pmu_disable, + }; + } /* Choose this cpu to collect perf data */ ddr_pmu->cpu = raw_smp_processor_id(); @@ -827,7 +848,7 @@ static void cn10k_ddr_perf_remove(struct platform_device *pdev) #ifdef CONFIG_OF static const struct of_device_id cn10k_ddr_pmu_of_match[] = { - { .compatible = "marvell,cn10k-ddr-pmu", }, + { .compatible = "marvell,cn10k-ddr-pmu", .data = &ddr_pmu_data}, { }, }; MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match); @@ -835,7 +856,7 @@ MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match); #ifdef CONFIG_ACPI static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] = { - {"MRVL000A", 0}, + {"MRVL000A", (kernel_ulong_t)&ddr_pmu_data}, {}, }; MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match);