| Message ID | 20240919094339.2407641-7-billy_tsai@aspeedtech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Aspeed G7 gpio support | expand |
On Thu, Sep 19, 2024 at 11:43 AM Billy Tsai <billy_tsai@aspeedtech.com> wrote: > Performing a dummy read ensures that the register write operation is fully > completed, mitigating any potential bus delays that could otherwise impact > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on > a delay function to ensure the clock frequency does not exceed 1 MHz. > However, this can lead to rapid toggling of the GPIO because the write > operation is POSTed and does not wait for a bus acknowledgment. > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> If this applies cleanly on mainline I think it should go into fixes as-is. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On Tue, Oct 1, 2024 at 4:18 PM Linus Walleij <linus.walleij@linaro.org> wrote: > > On Thu, Sep 19, 2024 at 11:43 AM Billy Tsai <billy_tsai@aspeedtech.com> wrote: > > > Performing a dummy read ensures that the register write operation is fully > > completed, mitigating any potential bus delays that could otherwise impact > > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to > > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application > > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on > > a delay function to ensure the clock frequency does not exceed 1 MHz. > > However, this can lead to rapid toggling of the GPIO because the write > > operation is POSTed and does not wait for a bus acknowledgment. > > > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> > > If this applies cleanly on mainline I think it should go into fixes as-is. > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > Yours, > Linus Walleij I agree but it doesn't. :( Billy: please send it separately and - while at it - use a C-style comment. Bart
> > > > On Thu, Sep 19, 2024 at 11:43 AM Billy Tsai <billy_tsai@aspeedtech.com> wrote: > > > > > Performing a dummy read ensures that the register write operation is fully > > > completed, mitigating any potential bus delays that could otherwise impact > > > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to > > > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application > > > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on > > > a delay function to ensure the clock frequency does not exceed 1 MHz. > > > However, this can lead to rapid toggling of the GPIO because the write > > > operation is POSTed and does not wait for a bus acknowledgment. > > > > > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> > > > > If this applies cleanly on mainline I think it should go into fixes as-is. > > > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > > > Yours, > > Linus Walleij > I agree but it doesn't. :( > Billy: please send it separately and - while at it - use a C-style comment. > Bart Hi Linus Walleij and Bart, Sorry, I don’t quite understand the meaning of “send it separately.” Does this mean I need to send this patch individually after the GPIO patch series has been accepted? Thanks Billy Tsai
On Wed, Oct 2, 2024 at 5:09 PM Billy Tsai <billy_tsai@aspeedtech.com> wrote: > > > > > > > On Thu, Sep 19, 2024 at 11:43 AM Billy Tsai <billy_tsai@aspeedtech.com> wrote: > > > > > > > Performing a dummy read ensures that the register write operation is fully > > > > completed, mitigating any potential bus delays that could otherwise impact > > > > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to > > > > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application > > > > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on > > > > a delay function to ensure the clock frequency does not exceed 1 MHz. > > > > However, this can lead to rapid toggling of the GPIO because the write > > > > operation is POSTed and does not wait for a bus acknowledgment. > > > > > > > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> > > > > > > If this applies cleanly on mainline I think it should go into fixes as-is. > > > > > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > > > > > Yours, > > > Linus Walleij > > > I agree but it doesn't. :( > > > Billy: please send it separately and - while at it - use a C-style comment. > > > Bart > > Hi Linus Walleij and Bart, > > Sorry, I don’t quite understand the meaning of “send it separately.” > Does this mean I need to send this patch individually after the GPIO patch series has been accepted? > This is a fix, meaning: it should go upstream now and get backported to stable branches. The other patches from this series will go in the next merge window in two months or so. So send this as the first patch in the series with an appropriate Fixes: tag or even send it entirely independently from the rest. Bart
> > > > > > > > On Thu, Sep 19, 2024 at 11:43 AM Billy Tsai <billy_tsai@aspeedtech.com> wrote: > > > > > > > > > Performing a dummy read ensures that the register write operation is fully > > > > > completed, mitigating any potential bus delays that could otherwise impact > > > > > the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to > > > > > control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application > > > > > sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on > > > > > a delay function to ensure the clock frequency does not exceed 1 MHz. > > > > > However, this can lead to rapid toggling of the GPIO because the write > > > > > operation is POSTed and does not wait for a bus acknowledgment. > > > > > > > > > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> > > > > > > > > If this applies cleanly on mainline I think it should go into fixes as-is. > > > > > > > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > > > > > > > Yours, > > > > Linus Walleij > > > > > I agree but it doesn't. :( > > > > > Billy: please send it separately and - while at it - use a C-style comment. > > > > > Bart > > > > Hi Linus Walleij and Bart, > > > > Sorry, I don’t quite understand the meaning of “send it separately.” > > Does this mean I need to send this patch individually after the GPIO patch series has been accepted? > > > This is a fix, meaning: it should go upstream now and get backported > to stable branches. The other patches from this series will go in the > next merge window in two months or so. So send this as the first patch > in the series with an appropriate Fixes: tag or even send it entirely > independently from the rest. > Bart Got it. Thanks for your prompt response. I will include this as the first patch in the next version. Billy Tsai
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index c811e84db0b9..daa12e21d946 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -400,6 +400,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, struct aspeed_gpio *gpio = gpiochip_get_data(gc); gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bits_get(gpio, offset, reg_val); } static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+)