From patchwork Thu Sep 19 09:43:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 13807622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 714D6CE8D68 for ; Thu, 19 Sep 2024 09:52:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To: From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=PXBR3WqY/xe8pQcWnDs1WNF7sGixG/iaEUh4WPOry8Y=; b=AynHDxHOQGXDp0VvVoZN70ar/Q O6hnzK6uTXyX5NEBVudzv7V55KuALugG3mxfMlUVgXjz2vPsv4yK/VxS35FnRqcc1euPlNgvUYcwc CZw8mEXm5dN4vBtc9Yl7r45X2pOaPwn5sEi3TNOvD1XEod/dGIo2CxSB1n6Nk1njuLqZ9tqoJMAR9 o+d0hb+j/5pbIvYYllvNTu4GdHvThFNGDKB2flI/+jeeOkClG2qvcISBfyP+2nqi847wbxVOLyR7F 3vvk+Nigjg1gmHvxcsny3rwc1fq9igr41AxWgKw5jANHpOEFqgaQUyia//T2xtxDonNuabrRoUMhF gKiCWSjQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1srDpz-00000009zY6-249n; Thu, 19 Sep 2024 09:52:35 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1srDhd-00000009xIp-0zR5 for linux-arm-kernel@lists.infradead.org; Thu, 19 Sep 2024 09:43:59 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 19 Sep 2024 17:43:39 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 19 Sep 2024 17:43:39 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , Subject: [PATCH v4 6/6] gpio: aspeed: Add the flush write to ensure the write complete. Date: Thu, 19 Sep 2024 17:43:39 +0800 Message-ID: <20240919094339.2407641-7-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240919094339.2407641-1-billy_tsai@aspeedtech.com> References: <20240919094339.2407641-1-billy_tsai@aspeedtech.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_024357_295420_5C5EC8B0 X-CRM114-Status: GOOD ( 10.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index c811e84db0b9..daa12e21d946 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -400,6 +400,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, struct aspeed_gpio *gpio = gpiochip_get_data(gc); gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bits_get(gpio, offset, reg_val); } static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,