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AJvYcCWQATCv8v/OpHXHny2TJuyzvkJ8z8O+Bj9cyLs2Y24G7Wx8hLRCl7eLEXwyPxOxkWeh/jdWVrEQm0SmTW3d//XI@lists.infradead.org X-Gm-Message-State: AOJu0YwG5+eL4AN+1MH7lCAHacm/5UhMKwQybmGthstYuAG3Yy9DkqKM 5qTalxazNkEuchdfx2T+VIeyP2nqckjgWHVm60TilF/sZW+Bd+1g X-Google-Smtp-Source: AGHT+IEhvS1/8bHcpqCM68pV2gaO+sQpYTUh6bBazzrIY3p1js5/1/bdomadlg6cx2Bh69svA1xScQ== X-Received: by 2002:a17:90a:5e0c:b0:2d8:f7e2:f03 with SMTP id 98e67ed59e1d1-2dba004842fmr30745184a91.32.1726762545103; Thu, 19 Sep 2024 09:15:45 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2dd6eed1865sm2084674a91.34.2024.09.19.09.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2024 09:15:44 -0700 (PDT) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Wim Van Sebroeck , Guenter Roeck , Catalin Marinas , Will Deacon , Lorenzo Pieralisi , Mark Kettenis , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Cc: konradybcio@kernel.org, ivo.ivanov.ivanov1@gmail.com, towinchenmi@gmail.com Subject: [PATCH v4 01/20] dt-bindings: arm: cpus: Add Apple A7-A11 CPU cores Date: Fri, 20 Sep 2024 00:05:50 +0800 Message-ID: <20240919161443.10340-2-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240919161443.10340-1-towinchenmi@gmail.com> References: <20240919161443.10340-1-towinchenmi@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_091546_621865_C88C2C07 X-CRM114-Status: GOOD ( 13.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the following CPU cores: - apple,cyclone: A7 cores - apple,typhoon: A8 cores - apple,twister: A9 cores - apple,hurricane-zephyr: A10 logical cores - apple,monsoon: A11 performance cores - apple,mistral: A11 efficiency cores In the Apple A10, there are physical performance-efficiency cores that forms logical cores to software depending on the current p-state, and only one type of core may be active at one time. This follows the existing newest-first order. Signed-off-by: Nick Chan --- Documentation/devicetree/bindings/arm/cpus.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index f308ff6c3532..f69b75afd258 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -87,8 +87,14 @@ properties: enum: - apple,avalanche - apple,blizzard - - apple,icestorm + - apple,cyclone - apple,firestorm + - apple,hurricane-zephyr + - apple,icestorm + - apple,mistral + - apple,monsoon + - apple,twister + - apple,typhoon - arm,arm710t - arm,arm720t - arm,arm740t