diff mbox series

[v1] arm64: dts: mediatek: mt8186: add FHCTL node

Message ID 20240923081340.860715-1-max_weng@compal.corp-partner.google.com (mailing list archive)
State New
Headers show
Series [v1] arm64: dts: mediatek: mt8186: add FHCTL node | expand

Commit Message

Max Weng Sept. 23, 2024, 8:13 a.m. UTC 
From: max_weng <max_weng@compal.corp-partner.google.com>

add fhctl device node.

Signed-off-by: max_weng <max_weng@compal.corp-partner.google.com>
---
 arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

AngeloGioacchino Del Regno Sept. 23, 2024, 8:35 a.m. UTC | #1 
Il 23/09/24 10:13, Max Weng ha scritto:
> From: max_weng <max_weng@compal.corp-partner.google.com>
> 
> add fhctl device node.

Please clarify the commit description, like so:

Add FHCTL device node for Frequency Hopping and Spread Spectrum
clocking function.

After which,
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>


> 
> Signed-off-by: max_weng <max_weng@compal.corp-partner.google.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 148c332018b0..d3c3c2a40adc 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -29,6 +29,13 @@ aliases {
>   		rdma1 = &rdma1;
>   	};
>   
> +	fhctl: fhctl@1000ce00 {
> +		compatible = "mediatek,mt8186-fhctl";
> +		clocks = <&apmixedsys CLK_APMIXED_TVDPLL>;
> +		reg = <0 0x1000ce00 0 0x200>;
> +		status = "disabled";
> +	};
> +
>   	cci: cci {
>   		compatible = "mediatek,mt8186-cci";
>   		clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 148c332018b0..d3c3c2a40adc 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -29,6 +29,13 @@  aliases {
 		rdma1 = &rdma1;
 	};
 
+	fhctl: fhctl@1000ce00 {
+		compatible = "mediatek,mt8186-fhctl";
+		clocks = <&apmixedsys CLK_APMIXED_TVDPLL>;
+		reg = <0 0x1000ce00 0 0x200>;
+		status = "disabled";
+	};
+
 	cci: cci {
 		compatible = "mediatek,mt8186-cci";
 		clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,