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[2001:b011:6c08:d055:c470:c180:5435:2e25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71944a974dcsm13991122b3a.32.2024.09.23.07.47.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Sep 2024 07:47:37 -0700 (PDT) From: Max Weng To: linux-kernel@vger.kernel.org Cc: max_weng@compal.corp-partner.google.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2] arm64: dts: mediatek: mt8186: add FHCTL node Date: Mon, 23 Sep 2024 22:47:28 +0800 Message-Id: <20240923144728.870285-1-max_weng@compal.corp-partner.google.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240923_074739_622912_E255D32B X-CRM114-Status: UNSURE ( 9.74 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: max_weng add FHCTL device node for Frequency Hopping and Spread Spectrum clock function. Change-Id: I7f9f2991978df7d5d3a6a8bc78f6f443f2f0460d Signed-off-by: Max Weng Reviewed-by: AngeloGioacchino Del Regno --- Change frome v1 to v2 * Modify the commit description arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 148c332018b0..d3c3c2a40adc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -29,6 +29,13 @@ aliases { rdma1 = &rdma1; }; + fhctl: fhctl@1000ce00 { + compatible = "mediatek,mt8186-fhctl"; + clocks = <&apmixedsys CLK_APMIXED_TVDPLL>; + reg = <0 0x1000ce00 0 0x200>; + status = "disabled"; + }; + cci: cci { compatible = "mediatek,mt8186-cci"; clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,