| Message ID | 20240926070405.20212-3-andy-ld.lu@mediatek.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add mtk-sd support for MT8196 | expand |
On Thu, Sep 26, 2024 at 03:03:18PM +0800, Andy-ld Lu wrote: > Extend the devicetree bindings to include the MT8196 mmc controller > by adding the compatible string 'mediatek,msdc-v2', which could be > also used for future compatible SoCs that support new tx/rx. > > Add three properties for MT8196 settings: > - 'mediatek,prohibit-gate-cg', indicate if the source clock CG could > be disabled when CPU access IP registers. > > - 'mediatek,stop-dly-sel', configure read data clock stops at block gap. > > - 'mediatek,pop-en-cnt', configure the margins of write and read > pointers while begin to pop data transfer. > > Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com> > --- > .../devicetree/bindings/mmc/mtk-sd.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml > index c532ec92d2d9..82d1a9fac67c 100644 > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml > @@ -25,6 +25,7 @@ properties: > - mediatek,mt8173-mmc > - mediatek,mt8183-mmc > - mediatek,mt8516-mmc > + - mediatek,msdc-v2 > - items: > - const: mediatek,mt7623-mmc > - const: mediatek,mt2701-mmc > @@ -154,6 +155,30 @@ properties: > enum: [32, 64] > default: 32 > > + mediatek,stop-dly-sel: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + Some SoCs need to set appropriate stop-dly-sel to configure read data clock > + stops at block gap. The valid range is from 0 to 0xf. If you used a specific compatible for these devices, which you should, you would not require either this or "pop-en-cnt". > + minimum: 0 > + maximum: 0xf > + > + mediatek,pop-en-cnt: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + Some SoCs need to set appropriate pop-en-cnt to configure the margins of write > + and read pointers while begin to pop data transfer. The valid range is from 0 > + to 0xf. > + minimum: 0 > + maximum: 0xf > + > + mediatek,prohibit-gate-cg: This is also probably detectable from a specific compatible, if you had one? TL;DR specific compatibles please, non of this "msdc-v2" stuff, sorry. Thanks, Conor. > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Decide if source clock CG could be disabled when CPU access IP registers. > + If present, source clock CG could not be disabled. > + If not present, source clock CG could be disabled. > + > resets: > maxItems: 1 > > @@ -191,6 +216,7 @@ allOf: > - mediatek,mt8188-mmc > - mediatek,mt8195-mmc > - mediatek,mt8516-mmc > + - mediatek,msdc-v2 > then: > properties: > clocks: > -- > 2.46.0 > >
On Thu, Sep 26, 2024 at 03:03:18PM +0800, Andy-ld Lu wrote: > Extend the devicetree bindings to include the MT8196 mmc controller > by adding the compatible string 'mediatek,msdc-v2', which could be > also used for future compatible SoCs that support new tx/rx. Generally, every SoC ends up changing at least slightly. So we don't do version numbers except when there's a well defined versioning scheme of the h/w (e.g. FPGA IP blocks). So, use SoC for compatible string. > > Add three properties for MT8196 settings: > - 'mediatek,prohibit-gate-cg', indicate if the source clock CG could > be disabled when CPU access IP registers. > > - 'mediatek,stop-dly-sel', configure read data clock stops at block gap. > > - 'mediatek,pop-en-cnt', configure the margins of write and read > pointers while begin to pop data transfer. > > Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com> > --- > .../devicetree/bindings/mmc/mtk-sd.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml > index c532ec92d2d9..82d1a9fac67c 100644 > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml > @@ -25,6 +25,7 @@ properties: > - mediatek,mt8173-mmc > - mediatek,mt8183-mmc > - mediatek,mt8516-mmc > + - mediatek,msdc-v2 > - items: > - const: mediatek,mt7623-mmc > - const: mediatek,mt2701-mmc > @@ -154,6 +155,30 @@ properties: > enum: [32, 64] > default: 32 > > + mediatek,stop-dly-sel: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + Some SoCs need to set appropriate stop-dly-sel to configure read data clock > + stops at block gap. The valid range is from 0 to 0xf. SoC dependent or board dependent? Imply from the compatible for the former. A property is fine for the latter case. > + minimum: 0 > + maximum: 0xf > + > + mediatek,pop-en-cnt: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + Some SoCs need to set appropriate pop-en-cnt to configure the margins of write > + and read pointers while begin to pop data transfer. The valid range is from 0 > + to 0xf. > + minimum: 0 > + maximum: 0xf Same question. > + > + mediatek,prohibit-gate-cg: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + Decide if source clock CG could be disabled when CPU access IP registers. > + If present, source clock CG could not be disabled. > + If not present, source clock CG could be disabled. Sounds like you need to describe the clock in "clocks". > + > resets: > maxItems: 1 > > @@ -191,6 +216,7 @@ allOf: > - mediatek,mt8188-mmc > - mediatek,mt8195-mmc > - mediatek,mt8516-mmc > + - mediatek,msdc-v2 > then: > properties: > clocks: > -- > 2.46.0 >
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index c532ec92d2d9..82d1a9fac67c 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8173-mmc - mediatek,mt8183-mmc - mediatek,mt8516-mmc + - mediatek,msdc-v2 - items: - const: mediatek,mt7623-mmc - const: mediatek,mt2701-mmc @@ -154,6 +155,30 @@ properties: enum: [32, 64] default: 32 + mediatek,stop-dly-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Some SoCs need to set appropriate stop-dly-sel to configure read data clock + stops at block gap. The valid range is from 0 to 0xf. + minimum: 0 + maximum: 0xf + + mediatek,pop-en-cnt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Some SoCs need to set appropriate pop-en-cnt to configure the margins of write + and read pointers while begin to pop data transfer. The valid range is from 0 + to 0xf. + minimum: 0 + maximum: 0xf + + mediatek,prohibit-gate-cg: + $ref: /schemas/types.yaml#/definitions/flag + description: + Decide if source clock CG could be disabled when CPU access IP registers. + If present, source clock CG could not be disabled. + If not present, source clock CG could be disabled. + resets: maxItems: 1 @@ -191,6 +216,7 @@ allOf: - mediatek,mt8188-mmc - mediatek,mt8195-mmc - mediatek,mt8516-mmc + - mediatek,msdc-v2 then: properties: clocks:
Extend the devicetree bindings to include the MT8196 mmc controller by adding the compatible string 'mediatek,msdc-v2', which could be also used for future compatible SoCs that support new tx/rx. Add three properties for MT8196 settings: - 'mediatek,prohibit-gate-cg', indicate if the source clock CG could be disabled when CPU access IP registers. - 'mediatek,stop-dly-sel', configure read data clock stops at block gap. - 'mediatek,pop-en-cnt', configure the margins of write and read pointers while begin to pop data transfer. Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com> --- .../devicetree/bindings/mmc/mtk-sd.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)