| Message ID | 20240927103005.17605-3-pablo.sun@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable Mali GPU on MediaTek Genio 700 EVK | expand |
Quoting Pablo Sun (2024-09-27 03:30:01) > Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated > mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when > setting mfgpll clock rate. > > If we keep the univpll parents from mfg_core_tmp, when setting > GPU frequency to 390000000, the common clock framework would switch > the parent to univpll, instead of setting mfgpll to 390000000: > > mfgpll 0 0 0 949999756 > univpll 2 2 0 2340000000 > univpll_d6 1 1 0 390000000 > top_mfg_core_tmp 1 1 0 390000000 > mfg_ck_fast_ref 1 1 0 390000000 > mfgcfg_bg3d 1 1 0 390000000 > > This results in failures when subsequent devfreq operations need to > switch to other frequencies. So remove univpll from the parent list. > > This solution is taken from commit 72d38ed720e9 ("clk: mediatek: > clk-mt8195-topckgen: Drop univplls from mfg mux parents") > > Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- Applied to clk-next
diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c b/drivers/clk/mediatek/clk-mt8188-topckgen.c index c4baf4076ed6..6b07abe9a8f5 100644 --- a/drivers/clk/mediatek/clk-mt8188-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c @@ -342,11 +342,14 @@ static const char * const dsp7_parents[] = { "univpll_d3" }; +/* + * MFG can be also parented to "univpll_d6" and "univpll_d7": + * these have been removed from the parents list to let us + * achieve GPU DVFS without any special clock handlers. + */ static const char * const mfg_core_tmp_parents[] = { "clk26m", - "mainpll_d5_d2", - "univpll_d6", - "univpll_d7" + "mainpll_d5_d2" }; static const char * const camtg_parents[] = {
Same as MT8195, MT8188 GPU clock is primarly supplied by the dedicated mfgpll. The clock "mfg_core_tmp" is only used as an alt clock when setting mfgpll clock rate. If we keep the univpll parents from mfg_core_tmp, when setting GPU frequency to 390000000, the common clock framework would switch the parent to univpll, instead of setting mfgpll to 390000000: mfgpll 0 0 0 949999756 univpll 2 2 0 2340000000 univpll_d6 1 1 0 390000000 top_mfg_core_tmp 1 1 0 390000000 mfg_ck_fast_ref 1 1 0 390000000 mfgcfg_bg3d 1 1 0 390000000 This results in failures when subsequent devfreq operations need to switch to other frequencies. So remove univpll from the parent list. This solution is taken from commit 72d38ed720e9 ("clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents") Signed-off-by: Pablo Sun <pablo.sun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/clk/mediatek/clk-mt8188-topckgen.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)