From patchwork Fri Sep 27 11:17:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 13814155 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63861CEBF97 for ; Fri, 27 Sep 2024 11:26:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tvMDuavOXr/z0rclmUpOH9wEZAO+TlklJMaHT5pGx+o=; b=0YjMhYc+NDDWqb4eTePHYyf6Ro pKz9HYVgtegCardCFA89bXGpjHdX4AaBP06OQTDsS6GJ6FeVYfMNLF4/UxE9KXP54ew5pNZvlKIjJ h8j78PqT+ml/PNaHXuQvUQgTCRTNOWMtmdozQ/9OM/XhkeRkvAh/IM1atlfib5YQqIw0wxcdtKE+l 364DqeDsC3EajhjBHSDA9LuT79+3E8xjZnf3FGDMo4wavoB/KILl5dbfdGeydmvjrUJxgneONMx4z O5eu1Qa6Dt5eE09o0rtFmJIaYTlrvXBOctSBnAlrBDQeyiS/i3kdlTcdpmXPz8F2p0b33CFnn6QdZ LlYBLKyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1su97A-0000000AwqB-3zog; Fri, 27 Sep 2024 11:26:24 +0000 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1su8zG-0000000AvV3-42Kl for linux-arm-kernel@lists.infradead.org; Fri, 27 Sep 2024 11:18:16 +0000 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 27 Sep 2024 19:17:45 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 27 Sep 2024 19:17:45 +0800 From: Billy Tsai To: , , , , , , , , , , , , , , Subject: [PATCH v6 6/7] gpio: aspeed: Add the flush write to ensure the write complete. Date: Fri, 27 Sep 2024 19:17:43 +0800 Message-ID: <20240927111744.3511373-7-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240927111744.3511373-1-billy_tsai@aspeedtech.com> References: <20240927111744.3511373-1-billy_tsai@aspeedtech.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240927_041815_018861_23DB2D76 X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO's high/low transitions will rely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai Reviewed-by: Andrew Jeffery --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index d6a35e230370..7cea3c5ba696 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -406,6 +406,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, struct aspeed_gpio *gpio = gpiochip_get_data(gc); gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bit_get(gpio, offset, reg_val); } static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,