| Message ID | 20240927201313.624762-4-sean.anderson@linux.dev (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: renesas: Add SD/OE pin properties (part B) | expand |
On Fri, Sep 27, 2024 at 10:13 PM Sean Anderson <sean.anderson@linux.dev> wrote: > Add SD/OE pin properties to the devicetree so that Linux can configure > the pin without relying on the OTP. This matches the register > configuration reported by Adam [1] as well as his analysis of the > schematic. > > [1] https://lore.kernel.org/linux-arm-kernel/CAHCN7x+tcvih1-kmUs8tVLCAk0Gnj11t0yEZLPWk3UBNyad7Jg@mail.gmail.com/ > > Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.13. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 5a14f116f7a1..a258ba0d6b4f 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -364,6 +364,8 @@ versaclock6_bb: clock-controller@6a { #clock-cells = <1>; clocks = <&x304_clk>; clock-names = "xin"; + idt,shutdown = <0>; + idt,output-enable-active = <0>; assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, <&versaclock6_bb 3>, <&versaclock6_bb 4>; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 68b04e56ae56..06ad9db420d6 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -166,6 +166,8 @@ versaclock5: versaclock_som@6a { #clock-cells = <1>; clocks = <&x304_clk>; clock-names = "xin"; + idt,shutdown = <0>; + idt,output-enable-active = <0>; /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */ assigned-clocks = <&versaclock5 1>, <&versaclock5 2>,
Add SD/OE pin properties to the devicetree so that Linux can configure the pin without relying on the OTP. This matches the register configuration reported by Adam [1] as well as his analysis of the schematic. [1] https://lore.kernel.org/linux-arm-kernel/CAHCN7x+tcvih1-kmUs8tVLCAk0Gnj11t0yEZLPWk3UBNyad7Jg@mail.gmail.com/ Signed-off-by: Sean Anderson <sean.anderson@linux.dev> --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 2 ++ arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 ++ 2 files changed, 4 insertions(+)