From patchwork Mon Sep 30 16:10:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kristina Martsenko X-Patchwork-Id: 13816677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B40CBCE8360 for ; Mon, 30 Sep 2024 16:18:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uPR3RziZuKgw0JuxPlPbdcHLNkyb4uoJFxL4j+YJLq4=; b=Kd18NXDhGYPOJECZbRF3BzPMYE 6wUHbzJ8NTC0EnjOj8epudjmit7eVCcluWyLMySge5SC16piODeWXqj1ZbEOxSU8Qk1NJL9NL5YSP KzR2bYgLV/B4Peb9V36l0n9WpWzUuhQc4InOAHxxM0bdIENMFzezjnWDcADyOnBnt5IM3FSVCdCuf IbYSy/uhKX+aq7DQS25wZq8ETwg2r0Swmae6LwimzwSHmgvmggW4a0Fq+3MOn7mQ6LyIAE6H2sYa3 p405uQSVfB7vybGPbaJGdR9CBPS3aeftqVsMVxW/RQYT0VEXxpag9gwNaqgFTxm4jgVkDC4Xoov+F oOQrOHzg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svJ60-00000000D5L-1a4C; Mon, 30 Sep 2024 16:18:00 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svJ1I-00000000Bqy-2O9g for linux-arm-kernel@lists.infradead.org; Mon, 30 Sep 2024 16:13:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8B6F6DA7; Mon, 30 Sep 2024 09:13:37 -0700 (PDT) Received: from e126864.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 82F2E3F58B; Mon, 30 Sep 2024 09:13:06 -0700 (PDT) From: Kristina Martsenko To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Robin Murphy , Marc Zyngier Subject: [PATCH 3/5] arm64: mops: Document booting requirement for HCR_EL2.MCE2 Date: Mon, 30 Sep 2024 17:10:49 +0100 Message-Id: <20240930161051.3777828-4-kristina.martsenko@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240930161051.3777828-1-kristina.martsenko@arm.com> References: <20240930161051.3777828-1-kristina.martsenko@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240930_091308_671521_8812E8E5 X-CRM114-Status: GOOD ( 10.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document that hypervisors must set HCR_EL2.MCE2 and handle MOPS exceptions when they migrate a vCPU to another type of CPU, as Linux may not be able to handle the exception at all times. As one example, when running under nested virtualization, KVM does not handle MOPS exceptions from the nVHE/hVHE EL2 hyp as the hyp is never migrated, so the host hypervisor needs to handle them. There may be other situations (now or in the future) where the kernel can't handle an unexpected MOPS exception, so require that the hypervisor handles them. Signed-off-by: Kristina Martsenko --- Documentation/arch/arm64/booting.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index b57776a68f15..db46af5b9f0f 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -385,6 +385,9 @@ Before jumping into the kernel, the following conditions must be met: - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1. + - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1. The exception + handler must set PSTATE.SS to 0b0. + For CPUs with the Extended Translation Control Register feature (FEAT_TCR2): - If EL3 is present: