From patchwork Tue Oct 1 13:50:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13818059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 078E1CEACC5 for ; Tue, 1 Oct 2024 14:05:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+RiEVv9lrx4YyqHyxsB3ROWaPDC/hC3gXVl4m3x5AHs=; b=BtkhHHMkw72ZDU4byaNPluc4/4 Iw/Ik1lS1IbmLsq2fJ5BRfHhJUFAvTx0rO0FkPPj39iOEtzLGOyThyxs9J5ZRFampLWZOwkuP5nb7 4HSeMEyOGzlVXXi646rVYn3ew+Z8EPVKKGPJX7ARa8gGRssO51/O4X9aTNgmsz6jipG6RCmKW01CF k7ACwmsRYLRvN33aEaSPjilAl6r4tGP3RofTcc386PUWHQYxZMlmHSqnbNyFLk/I156q7cNxpwp0B 1XiuNF3VkLqkSHsF1C34z2re+XM+3eozxs7RVnwnzb3SO+EnEsCA+tYulj2aFIIGyv/BpMGr4vDnv ah1Hod0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svdV9-000000033vF-1Y51; Tue, 01 Oct 2024 14:05:19 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1svdIB-000000030hx-3fSr for linux-arm-kernel@lists.infradead.org; Tue, 01 Oct 2024 13:51:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1727790715; x=1759326715; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=hZYncEl3PuX7Sc7txgxvih4Nm58EQ3JxK90o7N0HGc4=; b=FRo+BjFT0SuGDMd4cpyaQRlKoNh/VumIcwE12J5auJRC0d6whXhNgJg7 BZ8WJQSyxftSCC8vVrqMf2ciL3kOsrKMnZYeSSwV+DU53I6+OAGRFxZlP 0XclrcgB6R+m9vOYac/LTW1LJRu679NxQDiJNAUJEBLaHL0NIYenrPPFy o83v1bpPVb66CQ0fwZrl67UUcSz/3LV/Pwljx71EOyvkyenCI00GSkI+i Nqih4DgRZgrNS1CDfOM9WkhCndTrJX1uAklauFZI01PCnOktTZH0WsEii 0q03IRwA7Gq9LKl7zIYoxxkzg/bpTEAH69ohnkLCcA5i4d+C3SYiC/beO w==; X-CSE-ConnectionGUID: PEtbMb/SSnq9y/Yd81naGA== X-CSE-MsgGUID: ORqmDQhcRqS/k0bgg1X8vw== X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="199893173" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 01 Oct 2024 06:51:53 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 1 Oct 2024 06:51:42 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 1 Oct 2024 06:51:39 -0700 From: Daniel Machon Date: Tue, 1 Oct 2024 15:50:43 +0200 Subject: [PATCH net-next 13/15] net: sparx5: ops out PTP IRQ handler MIME-Version: 1.0 Message-ID: <20241001-b4-sparx5-lan969x-switch-driver-v1-13-8c6896fdce66@microchip.com> References: <20241001-b4-sparx5-lan969x-switch-driver-v1-0-8c6896fdce66@microchip.com> In-Reply-To: <20241001-b4-sparx5-lan969x-switch-driver-v1-0-8c6896fdce66@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lars Povlsen , "Steen Hegelund" , , , , Richard Cochran , , , , , CC: , , X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241001_065156_020021_BAFFF51B X-CRM114-Status: GOOD ( 13.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PTP registers are located in two different register targets on Sparx5 and lan969x. We can't handle this with the register macros, so ops out the handler. Signed-off-by: Daniel Machon Reviewed-by: Steen Hegelund --- drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 4 +++- drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c index bcdce23b735f..c5239e547c35 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -599,6 +599,7 @@ static void sparx5_board_init(struct sparx5 *sparx5) static int sparx5_start(struct sparx5 *sparx5) { u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + const struct sparx5_ops *ops = sparx5->data->ops; char queue_name[32]; u32 idx; int err; @@ -723,7 +724,7 @@ static int sparx5_start(struct sparx5 *sparx5) if (sparx5->ptp_irq >= 0) { err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, - NULL, sparx5_ptp_irq_handler, + NULL, ops->ptp_irq_handler, IRQF_ONESHOT, "sparx5-ptp", sparx5); if (err) @@ -987,6 +988,7 @@ static const struct sparx5_ops sparx5_ops = { .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, .get_sdlb_group = &sparx5_get_sdlb_group, .set_port_mux = &sparx5_port_mux_set, + .ptp_irq_handler = &sparx5_ptp_irq_handler, }; static const struct sparx5_match_data sparx5_desc = { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h index 6fe840dbaf98..eb71bba02a77 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -271,6 +271,8 @@ struct sparx5_ops { struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port, struct sparx5_port_config *conf); + + irqreturn_t (*ptp_irq_handler)(int irq, void *args); }; struct sparx5_main_io_resource {