From patchwork Tue Oct 1 13:50:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13818035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0719ACEACC1 for ; Tue, 1 Oct 2024 13:55:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IZ8z8BEXDZFI5wamju6iV9bT777GpodRpEiUuVPs2Ao=; b=aBx+ko2FR3C3oyHXJwiXvF6ftV 9D8SIH9BA1KBxMS3JpQXDmitJa8cDon35+yKTLdnKPlMcaSDfzl/PPviOKoeHd7x6iYiXGHPEpdoX yNjiw7NQAaIukHDDz5c/IO78f6VSXN0wmQEN698/SWp1YJz5beTByOZ521uGuaaW9JaRRq51ds3Yz fVcZZibytGip3w7lH/i+vwdgR1gd77L8iKBpBisTYpIXWaQKCcS2jrSrExOzO6aDOGmmZDY2TT4Ex 5/hofwum17m4MTIRXFvZ7IvWX0BETcUlgcnBgIhwRr8pS8Ghp7DxD/3CnfqoqaABGsWbi7ANBzgzp f81b7S0Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svdLT-000000031Xv-29sW; Tue, 01 Oct 2024 13:55:19 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1svdHk-000000030Ya-39tZ for linux-arm-kernel@lists.infradead.org; Tue, 01 Oct 2024 13:51:30 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1727790688; x=1759326688; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=GW0CkmxZUMAJyz2lueB7K5XdnpbRBVCw7BP5D2Sd928=; b=DwERKRSbDpTGsujxW+guR8rn1fTMiye53WMft8UfATiYVO6N/mBKFeEH iNZIOpiLWLqcP8GUsQA2Lbq9JK/C7MDV15mLj1PRStrwauwh0v8r6ZN78 hJobnnz4mx1QwQ8LGgoKdA8aQsmDuX/BQ3TikTtxQSEM6m/xS2LZTqvO+ 9rw/17JnRYHZ5WMYJ1W4bydQCJZ9gH3gAxHjlmPPjBh0z95j9C6rTcRaY BEkn7ssO1stzxZB6o9MMDV2GGljpXocvGDzkcFIV8nfOwfDC5leK0FKqR CXepeOO4nDihM1IrypXePuITsg6VwBy4VCXnYmiVegib7XWU7Ff2f+PZ6 Q==; X-CSE-ConnectionGUID: +oQdX0lcTd+VPfROt+JSQg== X-CSE-MsgGUID: BaVOSJnYTMCJaOZJSeNurg== X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="33057484" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 01 Oct 2024 06:51:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 1 Oct 2024 06:51:19 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 1 Oct 2024 06:51:16 -0700 From: Daniel Machon Date: Tue, 1 Oct 2024 15:50:36 +0200 Subject: [PATCH net-next 06/15] net: sparx5: add constants to match data MIME-Version: 1.0 Message-ID: <20241001-b4-sparx5-lan969x-switch-driver-v1-6-8c6896fdce66@microchip.com> References: <20241001-b4-sparx5-lan969x-switch-driver-v1-0-8c6896fdce66@microchip.com> In-Reply-To: <20241001-b4-sparx5-lan969x-switch-driver-v1-0-8c6896fdce66@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lars Povlsen , "Steen Hegelund" , , , , Richard Cochran , , , , , CC: , , X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241001_065128_938228_F988FA5A X-CRM114-Status: GOOD ( 13.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add new struct sparx5_consts, containing all the chip constants that are known to be different for Sparx5 and lan969x. Also add a macro to access the constants. Signed-off-by: Daniel Machon Reviewed-by: Steen Hegelund --- .../net/ethernet/microchip/sparx5/sparx5_main.c | 21 ++++++++++++++++++++ .../net/ethernet/microchip/sparx5/sparx5_main.h | 23 ++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c index 9a8d2e8c02a5..5f3690a59ac1 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -953,11 +953,32 @@ static const struct sparx5_regs sparx5_regs = { .fsize = sparx5_fsize, }; +static const struct sparx5_consts sparx5_consts = { + .n_ports = 65, + .n_ports_all = 70, + .n_hsch_l1_elems = 64, + .n_hsch_queues = 8, + .n_lb_groups = 10, + .n_pgids = 2113, /* (2048 + n_ports) */ + .n_sio_clks = 3, + .n_own_upsids = 3, + .n_auto_cals = 7, + .n_filters = 1024, + .n_gates = 1024, + .n_sdlbs = 4096, + .n_dsm_cal_taxis = 8, + .buf_size = 4194280, + .qres_max_prio_idx = 630, + .qres_max_colour_idx = 638, + .tod_pin = 4, +}; + static const struct sparx5_match_data sparx5_desc = { .iomap = sparx5_main_iomap, .iomap_size = ARRAY_SIZE(sparx5_main_iomap), .ioranges = 3, .regs = &sparx5_regs, + .consts = &sparx5_consts, }; static const struct of_device_id mchp_sparx5_match[] = { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h index 738b86999fd8..91f5a3be829e 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -51,6 +51,8 @@ enum sparx5_vlan_port_type { SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ }; +#define SPX5_CONST(const) sparx5->data->consts->const + #define SPX5_PORTS 65 #define SPX5_PORTS_ALL 70 /* Total number of ports */ @@ -238,6 +240,26 @@ struct sparx5_regs { const unsigned int *fsize; }; +struct sparx5_consts { + u32 n_ports; /* Number of front ports */ + u32 n_ports_all; /* Number of front ports + internal ports */ + u32 n_hsch_l1_elems; /* Number of HSCH layer 1 elements */ + u32 n_hsch_queues; /* Number of HSCH queues */ + u32 n_lb_groups; /* Number of leacky bucket groupd */ + u32 n_pgids; /* Number of PGID's */ + u32 n_sio_clks; /* Number of serial IO clocks */ + u32 n_own_upsids; /* Number of own UPSID's */ + u32 n_auto_cals; /* Number of auto calendars */ + u32 n_filters; /* Number of PSFP filters */ + u32 n_gates; /* Number of PSFP gates */ + u32 n_sdlbs; /* Number of service dual leaky buckets */ + u32 n_dsm_cal_taxis; /* Number of DSM calendar taxis */ + u32 buf_size; /* Amount of QLIM watermark memory */ + u32 qres_max_prio_idx; /* Maximum QRES prio index */ + u32 qres_max_colour_idx; /* Maximum QRES colour index */ + u32 tod_pin; /* PTP TOD pin */ +}; + struct sparx5_main_io_resource { enum sparx5_target id; phys_addr_t offset; @@ -246,6 +268,7 @@ struct sparx5_main_io_resource { struct sparx5_match_data { const struct sparx5_regs *regs; + const struct sparx5_consts *consts; const struct sparx5_main_io_resource *iomap; int ioranges; int iomap_size;