From patchwork Tue Oct 1 13:50:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13818060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF992CEACC6 for ; Tue, 1 Oct 2024 14:08:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3IIokWEjqMU27O/Pc1Bf82rL1cbBeEl+Y/9WR4VhDtc=; b=LfzrK1YvHFb3k3Hy7pyzp3ldQE 1MzQWFUi5KFuNRBjkAhW6xkUCO5urKBz0+Hp4e/3Ay4Cm/Z49Vkxhm6eSCgWCizP6THlniPBlKf20 7Ttfvn6S7j5Z386pHY2O23KmAwzA3Ue5nEb3huMYXBOf8P8ZXnyqIRKpBrhdWCMS9qidcL913GdYa xJJDe2Pl6FZz5dI5RCGUaHYlOzMd4X2a+URO5kJ6aAcyiLFHhgT6wqZ7lXK3nIkrXzYZoBio65vDu iUx/aPYS9PxS6vecMotJrAF6+3ruBxuo77HYfdyQ0lHLJuJD6fmwdVSt5mIM0A0z9hoPV1PB9tBN/ Yz4He2zg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svdXX-000000034Kc-1xBH; Tue, 01 Oct 2024 14:07:47 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1svdID-000000030jX-4AXz for linux-arm-kernel@lists.infradead.org; Tue, 01 Oct 2024 13:51:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1727790717; x=1759326717; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=cS1/Jb4bAW3LR0cuIrZX464ZGlD8jNzAc34k6vz3YWM=; b=A1dJKqYX40euUW3aduWQI21A478kRSghLPS0TLjI/HeE4vefVXiHYUbO JGZCuO72FVAjLI5SJ0KpLszatVJ3GOMIYqmVB02CNNc1nL+Q+FhSo8gfQ 2r4FvoXoKw/4Ctcu6xR5dump2BZ+k+ZkotgRdhSfTVEgbF5cdd2GG7RXX gGBnGpSejkCnvVzbaKxxhPMV4iTsxOqDsnnoywOH5cHatpYFg2a5RzLpD 4gFJiHu52qTZbRBRI+9XwWmSo6RPL41ZTaLBGdZ8mK/RnDxtFdPPOVFh4 sFiCsYm/PXTa5rIKbVIj8/pLCrMGPX4p7ZY/apKndqA6ruUCq1LQ1aKcw Q==; X-CSE-ConnectionGUID: Cvj7zfnKQLmxTbAcCPAKFQ== X-CSE-MsgGUID: RvII0DCaSLiALB5MIKUZjg== X-IronPort-AV: E=Sophos;i="6.11,167,1725346800"; d="scan'208";a="32447685" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 01 Oct 2024 06:51:56 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 1 Oct 2024 06:51:25 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 1 Oct 2024 06:51:23 -0700 From: Daniel Machon Date: Tue, 1 Oct 2024 15:50:38 +0200 Subject: [PATCH net-next 08/15] net: sparx5: use SPX5_CONST for constants which do not have a symbol MIME-Version: 1.0 Message-ID: <20241001-b4-sparx5-lan969x-switch-driver-v1-8-8c6896fdce66@microchip.com> References: <20241001-b4-sparx5-lan969x-switch-driver-v1-0-8c6896fdce66@microchip.com> In-Reply-To: <20241001-b4-sparx5-lan969x-switch-driver-v1-0-8c6896fdce66@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Lars Povlsen , "Steen Hegelund" , , , , Richard Cochran , , , , , CC: , , X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241001_065158_112450_6A39ACAE X-CRM114-Status: GOOD ( 12.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that we have indentified all the chip constants, update the use of them where a symbol is not defined for the constant. Constants are accessed using the SPX5_CONSTS macro. Note that this macro might hide the use of the *sparx5 context pointer. In such case, a comment is added. Signed-off-by: Daniel Machon Reviewed-by: Steen Hegelund --- drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c index 063f02fd36c3..4b3e6986af55 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -524,7 +524,7 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) sparx5, LRN_AUTOAGE_CFG_1); - for (idx = 0; idx < 3; idx++) + for (idx = 0; idx < SPX5_CONST(n_sio_clks); idx++) spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), GCB_SIO_CLOCK_SYS_CLK_PERIOD, sparx5, @@ -551,11 +551,15 @@ static int sparx5_qlim_set(struct sparx5 *sparx5) for (res = 0; res < 2; res++) { for (prio = 0; prio < 8; prio++) spx5_wr(0xFFF, sparx5, - QRES_RES_CFG(prio + 630 + res * 1024)); + QRES_RES_CFG(prio + + SPX5_CONST(qres_max_prio_idx) + + res * 1024)); for (dp = 0; dp < 4; dp++) spx5_wr(0xFFF, sparx5, - QRES_RES_CFG(dp + 638 + res * 1024)); + QRES_RES_CFG(dp + + SPX5_CONST(qres_max_colour_idx) + + res * 1024)); } /* Set 80,90,95,100% of memory size for top watermarks */ @@ -600,7 +604,7 @@ static int sparx5_start(struct sparx5 *sparx5) int err; /* Setup own UPSIDs */ - for (idx = 0; idx < 3; idx++) { + for (idx = 0; idx < SPX5_CONST(n_own_upsids); idx++) { spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx));