diff mbox series

[15/47] arm64/sysreg: Add register fields for SPMDEVAFF_EL1

Message ID 20241001024356.1096072-16-anshuman.khandual@arm.com (mailing list archive)
State New
Headers show
Series KVM: arm64: Enable FGU (Fine Grained Undefined) for FEAT_FGT2 registers | expand

Commit Message

Anshuman Khandual Oct. 1, 2024, 2:43 a.m. UTC 
This adds register fields for SPMDEVAFF_EL1 as per the definitions based
on DDI0601 2024-06.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 865de0549a07..5d76c0ddcb85 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -114,6 +114,18 @@  Res0	63:1
 Field	0	OSLK
 EndSysreg
 
+Sysreg	SPMDEVAFF_EL1	2	0	9	13	6
+Res0	63:40
+Field	39:32	Aff3
+Field	31	F0V
+Field	30	U
+Res0	29:25
+Field	24	MT
+Field	23:16	Aff2
+Field	15:8	Aff1
+Field	7:0	Aff0
+EndSysreg
+
 Sysreg ID_PFR0_EL1	3	0	0	1	0
 Res0	63:32
 UnsignedEnum	31:28	RAS