diff mbox series

[25/47] arm64/sysreg: Add register fields for SPMCR_EL0

Message ID	20241001024356.1096072-26-anshuman.khandual@arm.com (mailing list archive)
State	New
Headers	show Return-Path: <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org> From: Anshuman Khandual <anshuman.khandual@arm.com> To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual <anshuman.khandual@arm.com>, Oliver Upton <oliver.upton@linux.dev>, James Morse <james.morse@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org> Subject: [PATCH 25/47] arm64/sysreg: Add register fields for SPMCR_EL0 Date: Tue, 1 Oct 2024 08:13:34 +0530 Message-Id: <20241001024356.1096072-26-anshuman.khandual@arm.com> In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
Series	KVM: arm64: Enable FGU (Fine Grained Undefined) for FEAT_FGT2 registers \| expand [00/47] KVM: arm64: Enable FGU (Fine Grained Undefined) for FEAT_FGT2 registers [01/47] arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 [02/47] arm64/sysreg: Update register fields for ID_AA64DFR0_EL1 [03/47] arm64/sysreg: Update register fields for ID_AA64PFR0_EL1 [04/47] arm64/sysreg: Add register fields for ID_AA64DFR2_EL1 [05/47] arm64/sysreg: Add register fields for HDFGRTR2_EL2 [06/47] arm64/sysreg: Add register fields for HDFGWTR2_EL2 [07/47] arm64/sysreg: Add register fields for HFGITR2_EL2 [08/47] arm64/sysreg: Add register fields for HFGRTR2_EL2 [09/47] arm64/sysreg: Add register fields for HFGWTR2_EL2 [10/47] arm64/sysreg: Add register fields for MDSELR_EL1 [11/47] arm64/sysreg: Add register fields for PMSIDR_EL1 [12/47] arm64/sysreg: Add register fields for TRBIDR_EL1 [13/47] arm64/sysreg: Add register fields for TRBMPAM_EL1 [14/47] arm64/sysreg: Add register fields for PMSDSFR_EL1 [15/47] arm64/sysreg: Add register fields for SPMDEVAFF_EL1 [16/47] arm64/sysreg: Add register fields for PFAR_EL1 [17/47] arm64/sysreg: Add register fields for PMIAR_EL1 [18/47] arm64/sysreg: Add register fields for PMECR_EL1 [19/47] arm64/sysreg: Add register fields for PMUACR_EL1 [20/47] arm64/sysreg: Add register fields for PMCCNTSVR_EL1 [21/47] arm64/sysreg: Add register fields for SPMSCR_EL1 [22/47] arm64/sysreg: Add register fields for SPMACCESSR_EL1 [23/47] arm64/sysreg: Add register fields for PMICNTR_EL0 [24/47] arm64/sysreg: Add register fields for PMICFILTR_EL0 [25/47] arm64/sysreg: Add register fields for SPMCR_EL0 [26/47] arm64/sysreg: Add register fields for SPMOVSCLR_EL0 [27/47] arm64/sysreg: Add register fields for SPMOVSSET_EL0 [28/47] arm64/sysreg: Add register fields for SPMINTENCLR_EL1 [29/47] arm64/sysreg: Add register fields for SPMINTENSET_EL1 [30/47] arm64/sysreg: Add register fields for SPMCNTENCLR_EL0 [31/47] arm64/sysreg: Add register fields for SPMCNTENSET_EL0 [32/47] arm64/sysreg: Add register fields for SPMSELR_EL0 [33/47] arm64/sysreg: Add register fields for PMICNTSVR_EL1 [34/47] arm64/sysreg: Add register fields for SPMIIDR_EL1 [35/47] arm64/sysreg: Add register fields for SPMDEVARCH_EL1 [36/47] arm64/sysreg: Add register fields for SPMCFGR_EL1 [37/47] arm64/sysreg: Add register fields for PMSSCR_EL1 [38/47] arm64/sysreg: Add register fields for PMZR_EL0 [39/47] arm64/sysreg: Add register fields for SPMCGCR0_EL1 [40/47] arm64/sysreg: Add register fields for SPMCGCR1_EL1 [41/47] arm64/sysreg: Add register fields for MDSTEPOP_EL1 [42/47] arm64/sysreg: Add register fields for ERXGSR_EL1 [43/47] arm64/sysreg: Add register fields for SPMACCESSR_EL2 [44/47] arm64/sysreg: Add remaining debug registers affected by HDFGxTR2_EL2 [45/47] KVM: arm64: nv: Add FEAT_FGT2 registers access from virtual EL2 [46/47] KVM: arm64: nv: Add FEAT_FGT2 registers based FGU handling [47/47] KVM: arm64: nv: Add trap forwarding for FEAT_FGT2 described registers

Commit Message

Anshuman Khandual Oct. 1, 2024, 2:43 a.m. UTC

This adds register fields for SPMCR_EL0 as per the definitions based
on DDI0601 2024-06.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff mbox series

Patch

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 300c213f39da..770c7ae23ce8 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -165,6 +165,19 @@  Sysreg	PMCCNTSVR_EL1	2	0	14	11	7
 Field	63:0	CCNT
 EndSysreg
 
+Sysreg	SPMCR_EL0	2	3	9	12	0
+Res0	63:12
+Field	11	TR0
+Field	10	HDBG
+Field	9	FZ0
+Field	8	NA
+Res0	7:5
+Field	4	EX
+Res0	3:2
+Field	1	P
+Field	0	E
+EndSysreg
+
 Sysreg	SPMSCR_EL1	2	7	9	14	7
 Field	63:32	IMP_DEF
 Field	31	RAO