From patchwork Tue Oct 1 02:43:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13817406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57CA3CEB2E4 for ; Tue, 1 Oct 2024 03:39:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0jP5PteCV7RYDFuz+YheOPpzFJZaUlayhYR3p2aH7bQ=; b=Nxv4TXkUaoh5KwcPkOlNbsiTay gfM3kIQ34X8i8/ZmHseEHPJC2o1bnomH8CIgbKpuvSHl23QBM3F1jrpKaFviAWkLh2pY+9eEgrXbb 198XqJKB87hmwl8bYFOUwtOscMtPVUnJPY4d2mdc0AC1SLpcKiCMwAafTTiXfDkBVB7a7W4PpwRm2 ASL1UtmH87fBliCCtiQ0+zgE2SFHk7GhF35Q3buUqbHNS7UWDZuks9ii2MYx07pkkqkvc/D61ZOH+ bU/xmoZCiseqFvrCII/9yVLwN9zp2hg15mMEVMkzkYKKQ7uLXbRObNlwWVLHe4eMOrv4Nz8RJlCW4 1PVwYsdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svTiz-00000001Urk-0Kd4; Tue, 01 Oct 2024 03:38:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svSui-00000001O2j-1jbg for linux-arm-kernel@lists.infradead.org; Tue, 01 Oct 2024 02:47:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9150D367; Mon, 30 Sep 2024 19:47:29 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.16.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A96F33F58B; Mon, 30 Sep 2024 19:46:56 -0700 (PDT) From: Anshuman Khandual To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: Anshuman Khandual , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown Subject: [PATCH 44/47] arm64/sysreg: Add remaining debug registers affected by HDFGxTR2_EL2 Date: Tue, 1 Oct 2024 08:13:53 +0530 Message-Id: <20241001024356.1096072-45-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241001024356.1096072-1-anshuman.khandual@arm.com> References: <20241001024356.1096072-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240930_194700_512667_D4D7AD2F X-CRM114-Status: UNSURE ( 8.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The HDFGxTR2_EL2 registers trap a set of debug and trace related registers. Almost all of those register encodings have been added in the tools sysreg format. Let's also add all the remaining encodings which are formula based (and only that, because we really don't care about what these registers actually do at this stage). Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/sysreg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9ea97dddefc4..85cbce07ce77 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -270,6 +270,12 @@ #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2) #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1) +#define SYS_SPMEVCNTR_EL0(m) sys_reg(2, 3, 14, (0 | (m >> 3)), (m & 7)) +#define SYS_SPMEVTYPER_EL0(m) sys_reg(2, 3, 14, (2 | (m >> 3)), (m & 7)) +#define SYS_SPMEVFILTR_EL0(m) sys_reg(2, 3, 14, (4 | (m >> 3)), (m & 7)) +#define SYS_SPMEVFILT2R_EL0(m) sys_reg(2, 3, 14, (6 | (m >> 3)), (m & 7)) +#define SYS_PMEVCNTSVR_EL1(m) sys_reg(2, 0, 14, (8 | (m >> 3)), (m & 7)) + /* ETM */ #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)