| Message ID | 20241002-alarm-drop-down-e37c31e50a48@spud (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Redo PolarFire SoC's mailbox/clock devicestrees and related code | expand |
On Wed, 02 Oct 2024 11:48:05 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The first reg region in this binding is not exclusively for clocks, as > evidenced by the dual role of this device as a reset controller at > present. The first region is however better described by a simple-mfd > syscon, but this would have require a significant re-write of the > devicetree for the platform, so the easy way out was chosen when reset > support was first introduced. The region doesn't just contain clock and > reset registers, it also contains pinctrl and interrupt controller > functionality, so drop the region from the clock binding so that it can > be described instead by a simple-mfd syscon rather than propagate this > incorrect description of the hardware to the new pic64gx SoC. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- > 1 file changed, 22 insertions(+), 14 deletions(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2a..ee4f31596d978 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and reset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of the mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include <dt-bindings/clock/microchip,mpfs-clock.h> soc { - #address-cells = <2>; - #size-cells = <2>; - clkcfg: clock-controller@20002000 { + #address-cells = <1>; + #size-cells = <1>; + + clkcfg: clock-controller@3E001000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; + reg = <0x3E001000 0x1000>; clocks = <&ref>; #clock-cells = <1>; };