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Tue, 01 Oct 2024 22:16:31 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 2 Oct 2024 13:16:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 2 Oct 2024 13:16:26 +0800 From: Macpaul Lin To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yong Wu , "Joerg Roedel" , Will Deacon , Robin Murphy , Matthias Brugger , AngeloGioacchino Del Regno , "Rohit Agarwal" , , , , , , , Alexandre Mergnat CC: Bear Wang , Pablo Sun , Macpaul Lin , Macpaul Lin , "Sen Chu" , Chris-qj chen , MediaTek Chromebook Upstream , Chen-Yu Tsai Subject: [PATCH v5 2/5] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs Date: Wed, 2 Oct 2024 13:16:17 +0800 Message-ID: <20241002051620.2050-2-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241002051620.2050-1-macpaul.lin@mediatek.com> References: <20241002051620.2050-1-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.056800-8.000000 X-TMASE-MatchedRID: P0y1Pz0bU7nwBTQ+XvV6VYzb2GR6Ttd3YQXxsZnRwoIY0A95tjAn+9EQ LJPlYQqE0KHDXPxFjpCs8FHZk8InNB1YpEPWJiyzKaMQ6tw7oDLFUZ7q8HqQFFwpnAAvAwazMq+ en+OaNuuJTSQ4G0hWQLlh5xXch+ETbC1/2cudIH8ve6W+IORwrePmXK6rwg5BzsQ8iRVyD45ZoZ UwtnkREuLzNWBegCW2wgn7iDBesS1YF3qW3Je6+yJGz/iQlWEgbjQ3HsjeQ9VvX1BD59umeavcA mjImT522QK4L+FfNK00VrGYKV5cSQ2TVMfnleX9CaN5RfGxsx4o8fxKaOKaUoSVUZZHNLr+RgV6 Hsqyx11QaONuZ6Jr4g9k3l8EaYIcovpDXVQHzIN+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.056800-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 9854A0E68FA650A45118D093163C2FB7619D4D4BDDE09EA56A531646E776FEF52000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241001_221639_711116_06898CAD X-CRM114-Status: GOOD ( 13.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due to an excessively long 'interrupts' property. The error message was: infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long To address this issue, update the compatbile matching rule for 'interrupts' property. This change allows flexibility in the number of interrupts for new SoCs like MT8195. The purpose of these 5 interrupts is also added into description. Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema") Signed-off-by: Macpaul Lin --- .../bindings/iommu/mediatek,iommu.yaml | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) Changes for v2: - commit message: re-formatting and add a description of adding 5 interrupts. - add 'description' and 'maxItems: 5' for 'interrupt' property of 'mt8195-iommu-infra' - others keeps 'maxItems: 1' Changes for v3: - Refine the description for 'interrupts' property and fixes the compatible matching rules. - Refine commit message. Changes for v4: - add missing 'minItems: 5' to 'mediatek,mt8195-iommu-infra'. Thanks the explanation from Conor and Krzysztof. Changes for v5: - Repharse the description for interrupts property of MT8195. diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index ea6b0f5f24de..df8b2429008e 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -96,7 +96,16 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + description: | + Usually, the IOMMU requires only one interrupt. + + The infra IOMMU in MT8195 has five banks: each features one set + of APB registers. One for the normal world (set 0), three for the + protected world (sets 1-3), and one for the secure world (set 4). + and each set has its own interrupt. Therefore, five interrupts + are needed. + minItems: 1 + maxItems: 5 clocks: items: @@ -210,6 +219,24 @@ allOf: required: - mediatek,larbs + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-iommu-infra + + then: + properties: + interrupts: + minItems: 5 + maxItems: 5 + + else: + properties: + interrupts: + maxItems: 1 + additionalProperties: false examples: