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Wed, 02 Oct 2024 04:46:53 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b2652baefsm9639627b3a.180.2024.10.02.04.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 04:46:53 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 2/9] arm64: dts: mediatek: mt8188: Add PCIe nodes Date: Wed, 2 Oct 2024 19:41:42 +0800 Message-ID: <20241002114614.847553-3-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002114614.847553-1-fshao@chromium.org> References: <20241002114614.847553-1-fshao@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241002_124657_141986_1F01C319 X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add PCIe node and the associated PHY node. Individual board device tree should enable the nodes as needed. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 10195a4e4e9d..9431f3c5c228 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1763,6 +1763,53 @@ xhci0: usb@112b0000 { status = "disabled"; }; + pcie: pcie@112f0000 { + compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; + reg = <0 0x112f0000 0 0x2000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; + bus-range = <0 0xff>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", + "peri_26m", "peri_mem"; + + #interrupt-cells = <1>; + interrupts = ; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + + iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; + iommu-map-mask = <0>; + + phys = <&pcieport PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; + + resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; + reset-names = "mac"; + + status = "disabled"; + + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + nor_flash: spi@1132c000 { compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; reg = <0 0x1132c000 0 0x1000>; @@ -1775,6 +1822,21 @@ nor_flash: spi@1132c000 { status = "disabled"; }; + pciephy: t-phy@11c20700 { + compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; + ranges = <0 0 0x11c20700 0x700>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + pcieport: pcie-phy@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + i2c1: i2c@11e00000 { compatible = "mediatek,mt8188-i2c"; reg = <0 0x11e00000 0 0x1000>,