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AJvYcCW8BAz7X1+Dn0W+/juzWdQIq0fYeD8VH7ahuxPgrWdKKRxkO0gC2wkcoywLNiwVnCmKNkXIOMhWUzA0o1GyidA2@lists.infradead.org X-Gm-Message-State: AOJu0YxNHZ1wnllhQUHjVbGXmYM/en4rwtY4FxDt7NNA8xPyqRdhaCI7 2qDZp5DrY+lXqdBws+EebAsHRKKs+h55AKNIlU2Z2nQTr82KCYLwcDGBGALj5ps= X-Google-Smtp-Source: AGHT+IHWRZVOeFFozi3DIiPiL+943vH2vaAy8MMudke5kiB5y6RE2CXPLw9EOtOlNRxTNhpGiUSfiA== X-Received: by 2002:a05:600c:3b05:b0:42c:b750:19ce with SMTP id 5b1f17b1804b1-42f777b628fmr32913575e9.1.1727900174107; Wed, 02 Oct 2024 13:16:14 -0700 (PDT) Received: from gpeter-l.lan ([145.224.66.77]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cd564d2e8sm14850600f8f.18.2024.10.02.13.16.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 13:16:13 -0700 (PDT) From: Peter Griffin To: vkoul@kernel.org, kishon@kernel.org, krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Peter Griffin Subject: [PATCH 1/3] phy: Add UFS phy hibernate modes Date: Wed, 2 Oct 2024 21:15:53 +0100 Message-ID: <20241002201555.3332138-2-peter.griffin@linaro.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002201555.3332138-1-peter.griffin@linaro.org> References: <20241002201555.3332138-1-peter.griffin@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241002_131616_185458_DF4C45A7 X-CRM114-Status: GOOD ( 10.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some UFS phys need to write hibernation specific values when entering and exiting hibernate state. Add two new UFS phy modes to the phy framework so that this is possible. One such platform that requires this is Pixel 6 which uses the gs101 SoC. Signed-off-by: Peter Griffin --- include/linux/phy/phy.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 03cd5bae92d3..1874e55e2bb9 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -42,7 +42,9 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_UFS_HIBERN8_ENTER, + PHY_MODE_UFS_HIBERN8_EXIT, }; enum phy_media {