From patchwork Thu Oct 3 03:09:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 13820646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73B72CF8552 for ; Thu, 3 Oct 2024 03:11:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=oTm1fXXyNbEjaSytwTVBGR6jZI+/WfArELCCgciIDnY=; b=ey/8pvXBD9i5Ivg/Ttvbcf4uKH bSSBg/7NSE5/1fuk+LbdVdevSSN4gj7r4l3F63rqD0ZPQJABEc09hinhSnw5/2FLj2B66eqRygt+N 9bYMRvzdLv+mrSRCllk8McvTs4rG/7zRZmxYEjseauPqTeRdOdS9GO+tcfN0chsiI8anKDOaNC80B m881d4u0qSoBH1tL7OxbaHNIdp4XRFZdMshY5ufuVZv9msp9DHaaKxC6uJCRp5sIlbGUrRx1EpZXR f3h8B7HbmL68lzFgJQDB28i4wPiW/L0d2sQCaiGlv2+vxLNL2217y8SkfUssCSodtLlyoSq6FlCJy Fl+JrlIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1swCEv-000000083Fm-33Yi; Thu, 03 Oct 2024 03:10:53 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1swCDe-000000082vH-1UH6; Thu, 03 Oct 2024 03:09:35 +0000 X-UUID: e712290e813411efb3adad29d29602c1-20241002 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=oTm1fXXyNbEjaSytwTVBGR6jZI+/WfArELCCgciIDnY=; b=lMk1/Q3eD7+uKALsdTwMHkSTlX/m+pFHtSDSRqgSEEtoWd1NA7EVSBcIGq/l2oI2/gQzpG3PhdcFD2W10jlgKQF4sItO9L2i6vQnMxZ53nTBx1bOWasqO1J3E/Un47pE8BdmAYEw0tyjv8x3BgzbXwssXRdyA9LKs3ztuo7Ag6s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:5d30708e-ec0d-482f-842a-a16e5b495f24,IP:0,U RL:0,TC:0,Content:0,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:6dc6a47,CLOUDID:ac0ae51a-3b87-4dc0-9e4d-1d837ff4304b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:1|19,IP:nil ,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES: 1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: e712290e813411efb3adad29d29602c1-20241002 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1392029452; Wed, 02 Oct 2024 20:09:28 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 3 Oct 2024 11:09:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 3 Oct 2024 11:09:25 +0800 From: Macpaul Lin To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yong Wu , Joerg Roedel , Will Deacon , Robin Murphy , Matthias Brugger , AngeloGioacchino Del Regno , Rohit Agarwal , , , , , , , Alexandre Mergnat CC: Bear Wang , Pablo Sun , Macpaul Lin , Macpaul Lin , Sen Chu , Chris-qj chen , MediaTek Chromebook Upstream , Chen-Yu Tsai Subject: [PATCH v6 1/4] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs Date: Thu, 3 Oct 2024 11:09:16 +0800 Message-ID: <20241003030919.17980-1-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241002_200934_429790_16A40EDD X-CRM114-Status: GOOD ( 13.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due to an excessively long 'interrupts' property. The error message was: infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long To address this issue, update the compatbile matching rule for 'interrupts' property. This change allows flexibility in the number of interrupts for new SoCs like MT8195. The purpose of these 5 interrupts is also added into description. Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema") Signed-off-by: Macpaul Lin Reviewed-by: Rob Herring (Arm) --- .../bindings/iommu/mediatek,iommu.yaml | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) Changes for v2: - commit message: re-formatting and add a description of adding 5 interrupts. - add 'description' and 'maxItems: 5' for 'interrupt' property of 'mt8195-iommu-infra' - others keeps 'maxItems: 1' Changes for v3: - Refine the description for 'interrupts' property and fixes the compatible matching rules. - Refine commit message. Changes for v4: - add missing 'minItems: 5' to 'mediatek,mt8195-iommu-infra'. Thanks the explanation from Conor and Krzysztof. Changes for v5: - Repharse the description for interrupts property of MT8195. Changes for v6: - Remove maxItems for mt8195-iommu-infra. - Add 'Reviewed-by' tag from Rob. Thanks for the review. diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index ea6b0f5f24de..eeb39f5acf7e 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -96,7 +96,16 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + description: | + Usually, the IOMMU requires only one interrupt. + + The infra IOMMU in MT8195 has five banks: each features one set + of APB registers. One for the normal world (set 0), three for the + protected world (sets 1-3), and one for the secure world (set 4). + and each set has its own interrupt. Therefore, five interrupts + are needed. + minItems: 1 + maxItems: 5 clocks: items: @@ -210,6 +219,23 @@ allOf: required: - mediatek,larbs + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-iommu-infra + + then: + properties: + interrupts: + minItems: 5 + + else: + properties: + interrupts: + maxItems: 1 + additionalProperties: false examples: