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Signed-off-by: Frank Li --- Chagne from v1 to v2 - none --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 936ba5ecdcac7..9f643a4ce8ae7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -45,6 +45,15 @@ usb3_data_ss: endpoint { }; }; + reg_pcieb: regulator-pcie { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "mpcie_3v3"; + gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; @@ -246,6 +255,12 @@ &cm40_intmux { status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -272,6 +287,16 @@ &mu1_m0 { status = "okay"; }; +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; + &scu_key { status = "okay"; }; @@ -493,6 +518,14 @@ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 >; }; + pinctrl_pcieb: pcieagrp { + fsl,pins = < + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021 + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + pinctrl_typec: typecgrp { fsl,pins = < IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021