diff mbox series

[net-next] net: airoha: Fix EGRESS_RATE_METER_EN_MASK definition

Message ID 20241004-airoha-fixes-v1-1-2b7a01efc727@kernel.org (mailing list archive)
State New, archived
Headers show
Series [net-next] net: airoha: Fix EGRESS_RATE_METER_EN_MASK definition | expand

Commit Message

Lorenzo Bianconi Oct. 4, 2024, 9:51 p.m. UTC 
Fix typo in EGRESS_RATE_METER_EN_MASK mask definition. This bus was not
introducing any user visible problem.

Introduced by commit 23020f049327 ("net: airoha: Introduce ethernet support
for EN7581 SoC")

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/net/ethernet/mediatek/airoha_eth.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


---
base-commit: c55ff46aeebed1704a9a6861777b799f15ce594d
change-id: 20241004-airoha-fixes-8aaa8177b234

Best regards,

Comments

Jacob Keller Oct. 4, 2024, 10:49 p.m. UTC | #1 
On 10/4/2024 2:51 PM, Lorenzo Bianconi wrote:
> Fix typo in EGRESS_RATE_METER_EN_MASK mask definition. This bus was not
> introducing any user visible problem.
> 

I'm not sure I follow. This bit is used by airoha_qdma_init_qos which
sets the REG_EGRESS_RATE_METER_CFG register?

How does this not provide any user visible issues? It seems like an
incorrect enable bit likely means that QOS is not enabled? I'm guessing
bit 29 is reserved?

It would be good to understand why this is not considered a fix?  The
offending commit is in the net branch already.

> Introduced by commit 23020f049327 ("net: airoha: Introduce ethernet support
> for EN7581 SoC")
> 
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>  drivers/net/ethernet/mediatek/airoha_eth.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/mediatek/airoha_eth.c b/drivers/net/ethernet/mediatek/airoha_eth.c
> index 2e01abc70c170f32f4206b34e116b441c14c628e..a1cfdc146a41610a3a6b060bfdc6e1d9aad97d5d 100644
> --- a/drivers/net/ethernet/mediatek/airoha_eth.c
> +++ b/drivers/net/ethernet/mediatek/airoha_eth.c
> @@ -554,7 +554,7 @@
>  #define FWD_DSCP_LOW_THR_MASK		GENMASK(17, 0)
>  
>  #define REG_EGRESS_RATE_METER_CFG		0x100c
> -#define EGRESS_RATE_METER_EN_MASK		BIT(29)
> +#define EGRESS_RATE_METER_EN_MASK		BIT(31)
>  #define EGRESS_RATE_METER_EQ_RATE_EN_MASK	BIT(17)
>  #define EGRESS_RATE_METER_WINDOW_SZ_MASK	GENMASK(16, 12)
>  #define EGRESS_RATE_METER_TIMESLICE_MASK	GENMASK(10, 0)
> 
> ---
> base-commit: c55ff46aeebed1704a9a6861777b799f15ce594d
> change-id: 20241004-airoha-fixes-8aaa8177b234
> 
> Best regards,
Lorenzo Bianconi Oct. 5, 2024, 10:24 a.m. UTC | #2 
> 
> 
> On 10/4/2024 2:51 PM, Lorenzo Bianconi wrote:
> > Fix typo in EGRESS_RATE_METER_EN_MASK mask definition. This bus was not
> > introducing any user visible problem.
> > 
> 
> I'm not sure I follow. This bit is used by airoha_qdma_init_qos which
> sets the REG_EGRESS_RATE_METER_CFG register?
> 
> How does this not provide any user visible issues? It seems like an
> incorrect enable bit likely means that QOS is not enabled? I'm guessing
> bit 29 is reserved?

Hi Jacob,

even if we are setting EGRESS_RATE_METER_EN_MASK bit (with a wrong value) in
REG_EGRESS_RATE_METER_CFG register, egress QoS metering will not be supported
yet since we are missing some other configuration (token bucket rate, token
bucket size. Airoha folks please correct me if I am wrong). This is why I do
not think it is important to backport this patch and I did not added any Fixes
tag.
QoS hw ingress/egress metering is in my ToDo list. Here I have ported the basic
qos configuration I found in the vendor sdk. I will add more info in the commit
log in v2. Sorry for the confusion.

Regards,
Lorenzo

> 
> It would be good to understand why this is not considered a fix?  The
> offending commit is in the net branch already.
> 
> > Introduced by commit 23020f049327 ("net: airoha: Introduce ethernet support
> > for EN7581 SoC")
> > 
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >  drivers/net/ethernet/mediatek/airoha_eth.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/net/ethernet/mediatek/airoha_eth.c b/drivers/net/ethernet/mediatek/airoha_eth.c
> > index 2e01abc70c170f32f4206b34e116b441c14c628e..a1cfdc146a41610a3a6b060bfdc6e1d9aad97d5d 100644
> > --- a/drivers/net/ethernet/mediatek/airoha_eth.c
> > +++ b/drivers/net/ethernet/mediatek/airoha_eth.c
> > @@ -554,7 +554,7 @@
> >  #define FWD_DSCP_LOW_THR_MASK		GENMASK(17, 0)
> >  
> >  #define REG_EGRESS_RATE_METER_CFG		0x100c
> > -#define EGRESS_RATE_METER_EN_MASK		BIT(29)
> > +#define EGRESS_RATE_METER_EN_MASK		BIT(31)
> >  #define EGRESS_RATE_METER_EQ_RATE_EN_MASK	BIT(17)
> >  #define EGRESS_RATE_METER_WINDOW_SZ_MASK	GENMASK(16, 12)
> >  #define EGRESS_RATE_METER_TIMESLICE_MASK	GENMASK(10, 0)
> > 
> > ---
> > base-commit: c55ff46aeebed1704a9a6861777b799f15ce594d
> > change-id: 20241004-airoha-fixes-8aaa8177b234
> > 
> > Best regards,
>
Jacob Keller Oct. 8, 2024, 4:46 p.m. UTC | #3 
On 10/5/2024 3:24 AM, Lorenzo Bianconi wrote:
>>
>>
>> On 10/4/2024 2:51 PM, Lorenzo Bianconi wrote:
>>> Fix typo in EGRESS_RATE_METER_EN_MASK mask definition. This bus was not
>>> introducing any user visible problem.
>>>
>>
>> I'm not sure I follow. This bit is used by airoha_qdma_init_qos which
>> sets the REG_EGRESS_RATE_METER_CFG register?
>>
>> How does this not provide any user visible issues? It seems like an
>> incorrect enable bit likely means that QOS is not enabled? I'm guessing
>> bit 29 is reserved?
> 
> Hi Jacob,
> 
> even if we are setting EGRESS_RATE_METER_EN_MASK bit (with a wrong value) in
> REG_EGRESS_RATE_METER_CFG register, egress QoS metering will not be supported
> yet since we are missing some other configuration (token bucket rate, token
> bucket size. Airoha folks please correct me if I am wrong). This is why I do
> not think it is important to backport this patch and I did not added any Fixes
> tag.
> QoS hw ingress/egress metering is in my ToDo list. Here I have ported the basic
> qos configuration I found in the vendor sdk. I will add more info in the commit
> log in v2. Sorry for the confusion.
> 
> Regards,
> Lorenzo


Thanks for explaining.
diff mbox series

Patch

diff --git a/drivers/net/ethernet/mediatek/airoha_eth.c b/drivers/net/ethernet/mediatek/airoha_eth.c
index 2e01abc70c170f32f4206b34e116b441c14c628e..a1cfdc146a41610a3a6b060bfdc6e1d9aad97d5d 100644
--- a/drivers/net/ethernet/mediatek/airoha_eth.c
+++ b/drivers/net/ethernet/mediatek/airoha_eth.c
@@ -554,7 +554,7 @@ 
 #define FWD_DSCP_LOW_THR_MASK		GENMASK(17, 0)
 
 #define REG_EGRESS_RATE_METER_CFG		0x100c
-#define EGRESS_RATE_METER_EN_MASK		BIT(29)
+#define EGRESS_RATE_METER_EN_MASK		BIT(31)
 #define EGRESS_RATE_METER_EQ_RATE_EN_MASK	BIT(17)
 #define EGRESS_RATE_METER_WINDOW_SZ_MASK	GENMASK(16, 12)
 #define EGRESS_RATE_METER_TIMESLICE_MASK	GENMASK(10, 0)