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AJvYcCXMac9fsAURdIC8oqJv7bDaItzPINPs6cNeTI6LBPjL+SJNaOZ2peopPP7Tedvpm4taqdR7GVT7OQNR0M+X8i2g@lists.infradead.org X-Gm-Message-State: AOJu0YxqK4COfdkukl/rO87yDQM+QztlnPCuMI2Aa27bTGMJF8vTN5T7 49vG13EHzzezn7xEN7cNcRHbFWUAZlMtxwEHpqffx5E4lBJnhzA/ X-Google-Smtp-Source: AGHT+IGn7UgZ9BJ/TlkQ+E2HAb0XR+rspKCuaZMeClu6zEYk8ERChl9lG0s2Nk1ILro9xGQFJ0oStg== X-Received: by 2002:a17:902:690b:b0:20c:f3cf:50e6 with SMTP id d9443c01a7336-20fa9eb649bmr18804295ad.38.1729658689494; Tue, 22 Oct 2024 21:44:49 -0700 (PDT) Received: from nick-mbp.ust.hk ([182.153.135.7]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-20e7f0de3c3sm49983125ad.207.2024.10.22.21.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 21:44:49 -0700 (PDT) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Wim Van Sebroeck , Guenter Roeck , Catalin Marinas , Will Deacon , Lorenzo Pieralisi , Mark Kettenis , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Cc: Nick Chan , Krzysztof Kozlowski Subject: [PATCH v6 RESEND 01/20] dt-bindings: arm: cpus: Add Apple A7-A11 CPU cores Date: Wed, 23 Oct 2024 12:40:36 +0800 Message-ID: <20241023044423.18294-2-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241023044423.18294-1-towinchenmi@gmail.com> References: <20241023044423.18294-1-towinchenmi@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241022_214450_553765_6352D8ED X-CRM114-Status: GOOD ( 12.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the following CPU cores: - apple,cyclone: A7 cores - apple,typhoon: A8 cores - apple,twister: A9 cores - apple,hurricane-zephyr: A10 logical cores - apple,monsoon: A11 performance cores - apple,mistral: A11 efficiency cores In the Apple A10, there are physical performance-efficiency cores that forms logical cores to software depending on the current p-state, and only one type of core may be active at one time. Acked-by: Krzysztof Kozlowski Signed-off-by: Nick Chan --- Documentation/devicetree/bindings/arm/cpus.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index c54d20dd9d7e..dc0d219ff9d5 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -87,8 +87,14 @@ properties: enum: - apple,avalanche - apple,blizzard - - apple,icestorm + - apple,cyclone - apple,firestorm + - apple,hurricane-zephyr + - apple,icestorm + - apple,mistral + - apple,monsoon + - apple,twister + - apple,typhoon - arm,arm710t - arm,arm720t - arm,arm740t