[3/3] arm64: dts: imx8qm-ss-hsio: fix PCI and SATA clock indices

Commit Message

Frank Li Oct. 25, 2024, 10:08 p.m. UTC

The first argument of lpcg should indices, instead of index. Fix it by
use predefined macro.

Fixes: 9f7053f67c8a ("arm64: dts: imx8-ss-hsio: Add PCIe and SATA support")
Signed-off-by: Frank Li <[e-mail]>
---
Shanw:
Sorry, I miss check this again. If you like, you can squash to previous
patch
---
 .../arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index 59b6a670462c7..b1d0189a17258 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -24,9 +24,9 @@  pciea: pcie@5f000000 {
 		interrupt-names = "msi";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		clocks = <&pciea_lpcg 2>,
-			 <&pciea_lpcg 0>,
-			 <&pciea_lpcg 1>;
+		clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
+			 <&pciea_lpcg IMX_LPCG_CLK_4>,
+			 <&pciea_lpcg IMX_LPCG_CLK_5>;
 		clock-names = "dbi", "mstr", "slv";
 		bus-range = <0x00 0xff>;
 		device_type = "pci";
@@ -54,9 +54,9 @@  pcieb: pcie@5f010000 {
 		interrupt-names = "msi";
 		#address-cells = <3>;
 		#size-cells = <2>;
-		clocks = <&pcieb_lpcg 2>,
-			 <&pcieb_lpcg 0>,
-			 <&pcieb_lpcg 1>;
+		clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
+			 <&pcieb_lpcg IMX_LPCG_CLK_4>,
+			 <&pcieb_lpcg IMX_LPCG_CLK_5>;
 		clock-names = "dbi", "mstr", "slv";
 		bus-range = <0x00 0xff>;
 		device_type = "pci";
@@ -76,8 +76,8 @@  sata: sata@5f020000 {
 		compatible = "fsl,imx8qm-ahci";
 		reg = <0x5f020000 0x10000>;
 		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&sata_lpcg 0>,
-			 <&sata_crr4_lpcg 0>;
+		clocks = <&sata_lpcg IMX_LPCG_CLK_4>,
+			 <&sata_crr4_lpcg IMX_LPCG_CLK_4>;
 		clock-names = "sata", "sata_ref";
 		phy-names = "sata-phy", "cali-phy0", "cali-phy1";
 		power-domains = <&pd IMX_SC_R_SATA_0>;