| Message ID | 20241031083519.364313-1-maz@kernel.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: Expose ID_AA64ISAR1_EL1.XS to sanitised feature consumers | expand |
On Thu, Oct 31, 2024 at 08:35:19AM +0000, Marc Zyngier wrote: > Despite KVM now being able to deal with XS-tagged TLBIs, we still don't > expose these feature bits to KVM. > > Plumb in the feature in ID_AA64ISAR1_EL1. > > Fixes: 0feec7769a63 ("KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations") > Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Happy for this to go in as a fix via the kvm tree but let me know if I should pick it up instead.
On Fri, Nov 01, 2024 at 03:35:41PM +0000, Catalin Marinas wrote: > On Thu, Oct 31, 2024 at 08:35:19AM +0000, Marc Zyngier wrote: > > Despite KVM now being able to deal with XS-tagged TLBIs, we still don't > > expose these feature bits to KVM. > > > > Plumb in the feature in ID_AA64ISAR1_EL1. > > > > Fixes: 0feec7769a63 ("KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations") > > Signed-off-by: Marc Zyngier <maz@kernel.org> > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > > Happy for this to go in as a fix via the kvm tree but let me know if I > should pick it up instead. Thanks Catalin. I think this can wait for 6.13, would you mind grabbing it? If you do: Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
On Fri, 01 Nov 2024 15:35:41 +0000, Catalin Marinas <catalin.marinas@arm.com> wrote: > > On Thu, Oct 31, 2024 at 08:35:19AM +0000, Marc Zyngier wrote: > > Despite KVM now being able to deal with XS-tagged TLBIs, we still don't > > expose these feature bits to KVM. > > > > Plumb in the feature in ID_AA64ISAR1_EL1. > > > > Fixes: 0feec7769a63 ("KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations") > > Signed-off-by: Marc Zyngier <maz@kernel.org> > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > > Happy for this to go in as a fix via the kvm tree but let me know if I > should pick it up instead. No need to merge this urgently, nothing goes badly wrong. Thanks, M.
On Fri, Nov 01, 2024 at 08:47:48AM -0700, Oliver Upton wrote: > On Fri, Nov 01, 2024 at 03:35:41PM +0000, Catalin Marinas wrote: > > On Thu, Oct 31, 2024 at 08:35:19AM +0000, Marc Zyngier wrote: > > > Despite KVM now being able to deal with XS-tagged TLBIs, we still don't > > > expose these feature bits to KVM. > > > > > > Plumb in the feature in ID_AA64ISAR1_EL1. > > > > > > Fixes: 0feec7769a63 ("KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations") > > > Signed-off-by: Marc Zyngier <maz@kernel.org> > > > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > > > > Happy for this to go in as a fix via the kvm tree but let me know if I > > should pick it up instead. > > Thanks Catalin. I think this can wait for 6.13, would you mind grabbing > it? > > If you do: > > Reviewed-by: Oliver Upton <oliver.upton@linux.dev> I'll pick it up. Thanks.
On Thu, 31 Oct 2024 08:35:19 +0000, Marc Zyngier wrote: > Despite KVM now being able to deal with XS-tagged TLBIs, we still don't > expose these feature bits to KVM. > > Plumb in the feature in ID_AA64ISAR1_EL1. > > Applied to arm64 (for-next/misc), thanks! [1/1] arm64: Expose ID_AA64ISAR1_EL1.XS to sanitised feature consumers https://git.kernel.org/arm64/c/2287a4c1e118
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 718728a85430..db994d1fd97e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -228,6 +228,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
Despite KVM now being able to deal with XS-tagged TLBIs, we still don't expose these feature bits to KVM. Plumb in the feature in ID_AA64ISAR1_EL1. Fixes: 0feec7769a63 ("KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations") Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kernel/cpufeature.c | 1 + 1 file changed, 1 insertion(+)