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a=openpgp-sha256; l=3236; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=0ouY7CnsCCyHCfs0cERyo0bPhArCIHn61xKqJKfxl/o=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRrOcwT5L9bLK8i0xt/emHnss0n/bjY17rWrfEx/J+/I vSyjVFiRykLgxgHg6yYIsuOFZYr1P6oaUnc+FUMM4eVCWQIAxenAExkmjwjw9yvuwReCK7835J+ WebLvO33vk9waZ6uc7/m0Fq+3/xcB0sZGb4zKE9tipNjn7XQbw+jWNQOo7U/rzPf8/p89p/UlE9 bJVkB X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-Originating-IP: [172.25.16.114] X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=Q9aA4J2a c=1 sm=1 tr=0 ts=672a40aa cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=r_1tXGB3AAAA:8 a=iYL5nd4a90DRai7o0HQA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: 5QMsIHrlnVMs3GI4jtue8g3n5DfnXJag X-Proofpoint-ORIG-GUID: 5QMsIHrlnVMs3GI4jtue8g3n5DfnXJag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241105_155854_373065_99E919AD X-CRM114-Status: GOOD ( 14.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org With more than two firmware processor types, the if/else chain in pvr_fw_init() gets a bit ridiculous. Use a static array indexed on pvr_fw_processor_type (which is now a proper enum instead of #defines) instead. Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.h | 4 ---- drivers/gpu/drm/imagination/pvr_fw.c | 21 ++++++++++++++++----- drivers/gpu/drm/imagination/pvr_fw.h | 7 +++++++ 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h index 930129334807168cf11ee843f446eb5063464d55..ec5eb78af82a3f3c32d6c89b68b7bc0fcee0b9d2 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -738,8 +738,4 @@ pvr_ioctl_union_padding_check(void *instance, size_t union_offset, __union_size, __member_size); \ }) -#define PVR_FW_PROCESSOR_TYPE_META 0 -#define PVR_FW_PROCESSOR_TYPE_MIPS 1 -#define PVR_FW_PROCESSOR_TYPE_RISCV 2 - #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagination/pvr_fw.c index 808844eb10b5ccb29ed2b8e9bdfe3be829cc57d1..b77c4a42caf2f208f6289160e5cec36c683b1e65 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -926,16 +926,27 @@ pvr_fw_validate_init_device_info(struct pvr_device *pvr_dev) int pvr_fw_init(struct pvr_device *pvr_dev) { + static const struct pvr_fw_defs *fw_defs[PVR_FW_PROCESSOR_TYPE_COUNT] = { + [PVR_FW_PROCESSOR_TYPE_META] = &pvr_fw_defs_meta, + [PVR_FW_PROCESSOR_TYPE_MIPS] = &pvr_fw_defs_mips, + [PVR_FW_PROCESSOR_TYPE_RISCV] = NULL, + }; + u32 kccb_size_log2 = ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT; u32 kccb_rtn_size = (1 << kccb_size_log2) * sizeof(*pvr_dev->kccb.rtn); struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; int err; - if (fw_dev->processor_type == PVR_FW_PROCESSOR_TYPE_META) - fw_dev->defs = &pvr_fw_defs_meta; - else if (fw_dev->processor_type == PVR_FW_PROCESSOR_TYPE_MIPS) - fw_dev->defs = &pvr_fw_defs_mips; - else + if (fw_dev->processor_type >= PVR_FW_PROCESSOR_TYPE_COUNT) + return -EINVAL; + + fw_dev->defs = fw_defs[fw_dev->processor_type]; + + /* + * Not all firmware processor types are currently supported. + * Once they are, this check can be removed. + */ + if (!fw_dev->defs) return -EINVAL; err = fw_dev->defs->init(pvr_dev); diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagination/pvr_fw.h index 180d310074e3585c641e540a9e2576b5ab2a5705..88ad713468ce3a1ee459b04dde5363c24791a4f1 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -402,6 +402,13 @@ struct pvr_fw_device { #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_mask) +enum pvr_fw_processor_type { + PVR_FW_PROCESSOR_TYPE_META = 0, + PVR_FW_PROCESSOR_TYPE_MIPS, + PVR_FW_PROCESSOR_TYPE_RISCV, + PVR_FW_PROCESSOR_TYPE_COUNT, +}; + extern const struct pvr_fw_defs pvr_fw_defs_meta; extern const struct pvr_fw_defs pvr_fw_defs_mips;