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Tue, 5 Nov 2024 12:40:08 GMT Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 5 Nov 2024 04:40:05 -0800 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" CC: Tao Zhang , , , , , Mao Jinlong Subject: [PATCH v2 3/3] coresight-tpdm: Add support to enable the lane for MCMB TPDM Date: Tue, 5 Nov 2024 20:39:40 +0800 Message-ID: <20241105123940.39602-4-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241105123940.39602-1-quic_jinlmao@quicinc.com> References: <20241105123940.39602-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: XCCImNJbR_0os3Ug7-Zs0l-TP6mx89n1 X-Proofpoint-GUID: XCCImNJbR_0os3Ug7-Zs0l-TP6mx89n1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 phishscore=0 adultscore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411050097 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241105_044014_976494_F35232A3 X-CRM114-Status: GOOD ( 18.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Tao Zhang Add the sysfs file to set/get the enablement of the lane. For MCMB configurations, the field "E_LN" in CMB_CR register is the individual lane enables. MCMB lane N is enabled for trace generation when M_CMB_CR.E=1 and M_CMB_CR.E_LN[N]=1. For lanes that are not implemented on a given MCMB configuration, the corresponding bits of this field read as 0 and ignore writes. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 7 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 29 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 3 ++ 3 files changed, 39 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e833edfec79e..fcc2a8f1f17f 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -265,3 +265,10 @@ Contact: Tao Zhang (QUIC) Description: (RW) Set/Get which lane participates in the output pattern match cross trigger mechanism for the MCMB subunit TPDM. + +What: /sys/bus/coresight/devices//mcmb_lanes_select +Date: Nov 2024 +KernelVersion 6.13 +Contact: Tao Zhang (QUIC) +Description: + (RW) Set/Get the enablement of the individual lane. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 2e4dc86b03ea..bb0d6505ec9f 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -1063,6 +1063,34 @@ static ssize_t mcmb_trig_lane_store(struct device *dev, } static DEVICE_ATTR_RW(mcmb_trig_lane); +static ssize_t mcmb_lanes_select_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->cmb->mcmb.lane_select); +} + +static ssize_t mcmb_lanes_select_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val) || (val & ~TPDM_MCMB_E_LN_MASK)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + drvdata->cmb->mcmb.lane_select = val & TPDM_MCMB_E_LN_MASK; + + return size; +} +static DEVICE_ATTR_RW(mcmb_lanes_select); + static struct attribute *tpdm_dsb_edge_attrs[] = { &dev_attr_ctrl_idx.attr, &dev_attr_ctrl_val.attr, @@ -1227,6 +1255,7 @@ static struct attribute *tpdm_cmb_msr_attrs[] = { static struct attribute *tpdm_mcmb_attrs[] = { &dev_attr_mcmb_trig_lane.attr, + &dev_attr_mcmb_lanes_select.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index aa9746b2e77f..a80f3d680995 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -48,6 +48,9 @@ /* MAX lanes in the output pattern for MCMB configurations*/ #define TPDM_MCMB_MAX_LANES 8 +/* Filter bit 0~7 from the value for CR_E_LN */ +#define TPDM_MCMB_E_LN_MASK GENMASK(7, 0) + /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784)