| Message ID | 20241105224728.147384-1-marex@denx.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | ARM: dts: stm32: Increase CPU core voltage on STM32MP13xx DHCOR SoM | expand |
diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi index 07133bd82efa6..8630de147a52b 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -85,8 +85,8 @@ regulators { vddcpu: buck1 { /* VDD_CPU_1V2 */ regulator-name = "vddcpu"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection;
The STM32MP13xx DHCOR DHSBC is populated with STM32MP13xx part capable of 1 GHz operation, increase the CPU core voltage to 1.35 V to make sure the SoC is stable even if the blobs unconditionally force the CPU to 1 GHz operation. It is not possible to make use of CPUfreq on the STM32MP13xx because the SCMI protocol 0x13 is not implemented by upstream OpTee-OS which is the SCMI provider. Fixes: 6331bddce649 ("ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board") Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Marek Vasut <marex@denx.de> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: kernel@dh-electronics.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com --- arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)