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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, lftan.linux@gmail.com, leyfoon.tan@starfivetech.com Subject: [PATCH net-next v3 3/3] net: stmmac: dwmac4: Receive Watchdog Timeout is not in abnormal interrupt summary Date: Thu, 7 Nov 2024 14:36:36 +0800 Message-ID: <20241107063637.2122726-4-leyfoon.tan@starfivetech.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20241107063637.2122726-1-leyfoon.tan@starfivetech.com> References: <20241107063637.2122726-1-leyfoon.tan@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0034.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:c::11) To ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:f::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQZPR01MB0979:EE_|ZQZPR01MB0963:EE_ X-MS-Office365-Filtering-Correlation-Id: 4472be9e-78d2-47d4-dc54-08dcfef69afd X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|52116014|7416014|41320700013|38350700014; X-Microsoft-Antispam-Message-Info: ABEevHAuwl3TNStqcZmoJOJrTwnCKTvJYbM9sh8NnA8ZZWquheGxWlPrYPbdWdn/pJV4j1LM7CXChbikobN5DKWSmQOSck6WLiXjxD2Iaa+YW5SFzFDKpCSNhFPcIsyD4ck2lxW6KprNc3lkCX3ECGhBVruNzQxsUfMM7CvBIo98rEgmvoTe2RcBzhkMNZWMq1bOLkXrkvwcNLhft8F084dUYuIIh57GrtrKj1lvnela6zg+HLffodwcpWsEqBbSRC3ngdV9aDWoteybN6aQQLZ+Tqz8ONLAYmelQiCEN/y/s5gz8swaAtXZDS+3/iKdnOkAzTBPEcU07vyhAIDym26lzrlmW3Hvdw51tr10Yf9uwdy2fJGJTtPU9OJkXWLuuip1c0G6Tn4Vn7WzwgC27SNvPOSvfqQhO3oJNl4yZiCM8pUmkisDg5ZwFRW7SJM9EtwiXxJzjigUuOe8oKm8sD0WQ4JGabTyenLTYdTgOt/QfYEF4z8Xa9nVxWUVV3BXJqAkK5WX07iGTrlTcJ/UT7DtoMEwp2G0SV2cYBILP6WIfMvRsGqHBMGvSC8M8E783h7+rDFySLfMpHpOA617+4RX/9W5CE+jLCqPQ0ai3syPQ3QvEqVbDTMdgM9NEY1x X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(52116014)(7416014)(41320700013)(38350700014);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MVNOjN4p7Lhw5D5ADRVY06mJyPRsEONHxoc1Z8KR38WMLMhVkYZdb99uvcT02DU4ur8092nSJZkVZii5LGcxVFppdZDN+BHu4hE86whJEMhUguwWqik+bFh+0BPNSrQqGWErtZCTr022F1C5twamo9x0uerqBhXy8MLn+25VjjDiZjc75sPx7vww/lNndh/b8XFwDbbJUAOngKRGMU2MzFo4On0n6LKfq7LVqtFmbdY+9iGXrgNwkthYPfM/Hm70Z318UVHIB78hb31U1g9MkI6ql+XrfNOD9wRinmEBoN1kdaSuWDg3G9HIqipgOuxYTVbtgGht1oo0xyIg3aXkFPl2/F3hrkWEQzHN2FEpxNIBQbDpImXpoikMDqxXCkvCOUknu16/aGBkmCwQ9fGFXyypKJ9uMI8Qoc2Rj6zn4COMjEwZhYXQ/iUeOnRAfq9hTOe7AfsXklqle0F+PLGDi23593o9MxiJQ364aoRgHFY9je88WtbfoyqReqq+w+FGQd2nbygBXwOk+mNhpMkWdxoe74uGieEkKynlXHEy73YQeIfEL+MY6puoN8fRhM7d5KpogeVCXw8XYQY55C/YQpX1VWNA0X4aHaRBqbAtiuOFw4DYFuHehIuN5nm2ZYVSxM4www1wl/WOPlTRE1/bPixILUw1tmvk5ksV4ixd0OHCp2ytUJO3K7Mvr7SuvrkJQyC2cxtsgfvMH401KSp2DzfiHXfUqAgsuPDlY8NobV2dVkC6434T33p1ZBDQLLmIMUiM+KSgBV4v0IdKdQDoXJ4X4jkz29Tm2QC+SnvTY8Yu6qd8CB0IsfsE8UmjivtrjKp3/Vl7upYIVHZEnSYDB6vbMXZYKk2PNVILxp9xahP/+7Y2ot9k2lTDCDRvsu6MqRuSPIgdY56bQt4n0qKYfWWpIxFJ+BLbTZemYVf0DSv3ZiQXYPgTeow3xZPWBDl/y/SlsoEOJ8G5e9Rywb3Z5cge+GHteVq8HKfK5ElyNfIOdLzWnA6fwMRD9Q6lf+GyNqbsdd0LwxVSFYbMgVn/vNE3lDJtLz70VEqV+ox7BSF/1gjLWaKAIOB4KJeG6A7598K+bozTnPY66nBPXenALN/WIP/M9YD+ciJdBrwPWHa73LopQtRsYkhYzwAFRzVCjFzb3oJSfRW3x3T0Dm5WcVX0gp11l/ilrEdj9q2w9dvmZJm8zYYxWVe8zSkmiv+HS16hx8/vwJTPIjJ1Ff7ZAL6FXM+sS74PIU/pu/9cpyPZf6JrDtuz9DLBWdrcXVJQaczAGmlQtvgEUns8W2EtnPxkqCgFrGtsxhdQbLX+w+h4xALugxSFPRhG80zmCIRaGHG92u5dTxphrqOGGn56ZsTgn0QCMF/iqSGzp6fx2rd/ahzCE66YN9JPaFIKYYGythJh7ZINBsj9VJ4ITcdTqXb+d4Gh0mgT67pbCVcA52HU4ioldcNf85GpKkBgP3bkt1uEcV+FpkEGBLbIldV/ueEERboLhQaXkGucl8Rg++eROgoCsXYhe7gkzEDPN54hpqVfr7CPLBJjPw7Ja/Av5wnaPXl25V2JENKCsStr93YqOxACNMQPNsIKZ78EcbzMmTLrhLUBerpoRBe3r8tYwQ== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4472be9e-78d2-47d4-dc54-08dcfef69afd X-MS-Exchange-CrossTenant-AuthSource: ZQZPR01MB0979.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 06:37:09.7260 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: SadKhuLxLG6To0GP9RptRsz2TrGhdJ50YRxxUfZFnq2Lq7wxPnaKjELEL1VtnI/cHz3ATnGP7MYguHyFTTkonkm9DkOb+5OyYNH6U5pJTQg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: ZQZPR01MB0963 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241106_223704_537327_F3A109A7 X-CRM114-Status: UNSURE ( 8.50 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Receive Watchdog Timeout (RWT, bit[9]) is not part of Abnormal Interrupt Summary (AIS). Move the RWT handling out of the AIS condition statement. From databook, the AIS is the logical OR of the following interrupt bits: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context Descriptor Error Signed-off-by: Ley Foon Tan --- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c index 0d185e54eb7e..57c03d491774 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c @@ -185,8 +185,6 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, x->rx_buf_unav_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_RPS)) x->rx_process_stopped_irq++; - if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) - x->rx_watchdog_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_ETI)) x->tx_early_irq++; if (unlikely(intr_status & DMA_CHAN_STATUS_TPS)) { @@ -198,6 +196,10 @@ int dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, ret = tx_hard_error; } } + + if (unlikely(intr_status & DMA_CHAN_STATUS_RWT)) + x->rx_watchdog_irq++; + /* TX/RX NORMAL interrupts */ if (likely(intr_status & DMA_CHAN_STATUS_RI)) { u64_stats_update_begin(&stats->syncp);