@@ -1227,6 +1227,10 @@ icssg0: icssg@30000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x30000000 0x80000>;
+ clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
+ <&k3_clks 81 20>; /* icssg0_iclk */
+ assigned-clocks = <&k3_clks 81 0>;
+ assigned-clock-parents = <&k3_clks 81 2>;
icssg0_mem: memories@0 {
reg = <0x0 0x2000>,
@@ -1252,7 +1256,7 @@ icssg0_coreclk_mux: coreclk-mux@3c {
clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
<&k3_clks 81 20>; /* icssg0_iclk */
assigned-clocks = <&icssg0_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 81 20>;
+ assigned-clock-parents = <&k3_clks 81 0>;
};
icssg0_iepclk_mux: iepclk-mux@30 {
@@ -1397,6 +1401,10 @@ icssg1: icssg@30080000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x30080000 0x80000>;
+ clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
+ <&k3_clks 82 20>; /* icssg1_iclk */
+ assigned-clocks = <&k3_clks 82 0>;
+ assigned-clock-parents = <&k3_clks 82 2>;
icssg1_mem: memories@0 {
reg = <0x0 0x2000>,
@@ -1422,7 +1430,7 @@ icssg1_coreclk_mux: coreclk-mux@3c {
clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
<&k3_clks 82 20>; /* icssg1_iclk */
assigned-clocks = <&icssg1_coreclk_mux>;
- assigned-clock-parents = <&k3_clks 82 20>;
+ assigned-clock-parents = <&k3_clks 82 0>;
};
icssg1_iepclk_mux: iepclk-mux@30 {
ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at 333MHz. ICSSG_CORE clock will help get the most out of ICSSG as more cycles are needed to fully support all ICSSG features. This commit also changes assigned-clock-parents of coreclk-mux to ICSSG_CORE clock from ICSSG_ICLK. Performance update in dual mac mode With ICSSG_CORE Clk @ 333MHz Tx throughput - 934 Mbps Rx throuhput - 914 Mbps, With ICSSG_ICLK clk @ 250MHz, Tx throughput - 920 Mbps Rx throughput - 706 Mbps Signed-off-by: MD Danish Anwar <danishanwar@ti.com> --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)