From patchwork Tue Nov 12 10:37:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13872101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53F0CD32D91 for ; Tue, 12 Nov 2024 11:12:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=rUBQf8hA2fpU+kmR16EcISA5nfxhUZdSES5iWO7fp+4=; b=hi2tTLsjvR9iukZ+DqWpts5PoR +ZGAgYt+5wt46e5PJgf6TpH7bYicT2AvAqfBnIeX8zLtSzp67HdDnSMSPE08jVgu8b7FLNMF6mB23 1gCzCy8eKhAQlo7jwCUvFEvNEfgcVLWYIPjPHr/3LpQSY+FTws1lBKcdpC4OiPzdA3zGKzvyiEuXU 7fqXAh1nfzGNTv0VGEXT4uM+mfGwWiZTpLHxB1M6OfzLtjKsZ0fnd1eRMP8ud1eoGZtI38mpGn3TQ +kVZHWwdipuRkxeCibIml1kfJY/2Iz0TOtij1cXsuUl0Nqn1OGQldgcQNIJf0tUXoGGMdZ2FyYnAV Ri6aTAZQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tAooL-00000003ApM-11Cr; Tue, 12 Nov 2024 11:11:53 +0000 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tAoHS-000000034cX-2kov for linux-arm-kernel@lists.infradead.org; Tue, 12 Nov 2024 10:37:56 +0000 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-431ac30d379so47547465e9.1 for ; Tue, 12 Nov 2024 02:37:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731407873; x=1732012673; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rUBQf8hA2fpU+kmR16EcISA5nfxhUZdSES5iWO7fp+4=; b=iOkdzVbvkCiezurxyjPi9OUWvN965moWV4r+MwkwEkf3VW3ZoTizHdNFwlGbA7Yxgt 9kIuTwCIaKpVjAGEUUupUox13ktMHbsiKPRelMR9bOSadnAwGdtBEnJqFPY33VthyoGk 7Q7E0PtwKYRNIwNc/7NO9Yn3ZFwDQgQ3OncuAPeUmDSPn7qrmqhvBf9h/pXYWs2dKyXl k1gfW+8QesbE9WpBaZ81PznYrET1zbT1KzeCTKH7JvQKHAh0UZRbGGZJ0AHQagZfAZAU P+vGUwlgBs0SsAvEYDTLOliyuyBscQPAEwJerGxBrH5x0/7XICHFzOacWA8Za5MWjs/2 KnxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731407873; x=1732012673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rUBQf8hA2fpU+kmR16EcISA5nfxhUZdSES5iWO7fp+4=; b=VMlrMIvWsuKROW5GFWT2BwEL8WRmC7ZSpPHyFoJK+AsNmsGrdaJnviAckX5bWKLH/q Vqpcyvj1Y1IaLgawNKqkqDIsk+Rr00AjGBiSJMa5YxJpR52i3SY/lLrhYdNDuwbIgEem ESVU2HxQDdyaooj+jaLv0kbIEySdJRzpMroCcnPI5x3y6QYxMw9fi+D1zi1Lk2JAkNt5 rMkE/Y3aRvPt1A8nOHdDf/NhlsALhOsAfqHUFxoiFEg+75hAnWWRTAyxeAqugNeT9kok 1UXfJFbnhgQeItQgPUhWvTsU5QRCvBH4mgsapw/l5jtPiLDdCMjfCshA+C1sleCeyUF8 0uPw== X-Forwarded-Encrypted: i=1; AJvYcCX8FiC9HvA9TtkkrspnYIlm24ySCk3k7qRdrDp4r4EqIk1cHOHGC8txlSRf73NMlo7nHM7LtZ2SSc6U1Z9USpRY@lists.infradead.org X-Gm-Message-State: AOJu0Yz+eP+/9KhjZsqrSPkrZFm6Z/Uswm5POJFlJDEiOh71vh/Qe6SS f64aZxBWYmD/pYWrWljBErO7cIp3sLJ8jufuetEhv2U08vJd46sMB+VLDzhwZgU= X-Google-Smtp-Source: AGHT+IGEJl+Jco8dYWeX7p5xX2ZqQ1FJqfj/h/+GHbI4ME8cH4NEto1wKbqbA+SxHv+BKuc1PuLyIg== X-Received: by 2002:a05:600c:4f04:b0:42e:d4a2:ce67 with SMTP id 5b1f17b1804b1-432b7505d19mr149731975e9.17.1731407873250; Tue, 12 Nov 2024 02:37:53 -0800 (PST) Received: from pop-os.. ([145.224.90.214]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432bbf436ffsm142270955e9.44.2024.11.12.02.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 02:37:52 -0800 (PST) From: James Clark To: suzuki.poulose@arm.com, oliver.upton@linux.dev, coresight@lists.linaro.org, kvmarm@lists.linux.dev Cc: James Clark , Mark Brown , James Clark , Marc Zyngier , Joey Gouly , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Alexander Shishkin , Mark Rutland , Anshuman Khandual , "Rob Herring (Arm)" , James Morse , Shiqi Liu , Fuad Tabba , Raghavendra Rao Ananta , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 03/12] arm64/sysreg/tools: Move TRFCR definitions to sysreg Date: Tue, 12 Nov 2024 10:37:02 +0000 Message-Id: <20241112103717.589952-4-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112103717.589952-1-james.clark@linaro.org> References: <20241112103717.589952-1-james.clark@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241112_023754_803354_A85FC054 X-CRM114-Status: GOOD ( 14.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: James Clark Convert TRFCR to automatic generation. Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous definition so no code change is required. Also add TRFCR_EL12 which will start to be used in a later commit. Unfortunately, to avoid breaking the Perf build with duplicate definition errors, the tools copy of the sysreg.h header needs to be updated at the same time rather than the usual second commit. This is because the generated version of sysreg (arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared and tools/ does not have its own copy. Reviewed-by: Mark Brown Signed-off-by: James Clark Signed-off-by: James Clark --- arch/arm64/include/asm/sysreg.h | 12 --------- arch/arm64/tools/sysreg | 36 +++++++++++++++++++++++++++ tools/arch/arm64/include/asm/sysreg.h | 12 --------- 3 files changed, 36 insertions(+), 24 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 345e81e0d2b3..150416682e2c 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -283,8 +283,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -519,7 +517,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) @@ -983,15 +980,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a26c0da0c42d..27a7afd5329a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1994,6 +1994,22 @@ Sysreg CPACR_EL1 3 0 1 0 2 Fields CPACR_ELx EndSysreg +SysregFields TRFCR_ELx +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4:2 +Field 1 ExTRE +Field 0 E0TRE +EndSysregFields + +Sysreg TRFCR_EL1 3 0 1 2 1 +Fields TRFCR_ELx +EndSysreg + Sysreg SMPRI_EL1 3 0 1 2 4 Res0 63:4 Field 3:0 PRIORITY @@ -2536,6 +2552,22 @@ Field 1 ICIALLU Field 0 ICIALLUIS EndSysreg +Sysreg TRFCR_EL2 3 4 1 2 1 +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0000 USE_TRFCR_EL1_TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4 +Field 3 CX +Res0 2 +Field 1 E2TRE +Field 0 E0HTRE +EndSysreg + + Sysreg HDFGRTR_EL2 3 4 3 1 4 Field 63 PMBIDR_EL1 Field 62 nPMSNEVFR_EL1 @@ -2946,6 +2978,10 @@ Sysreg ZCR_EL12 3 5 1 2 0 Fields ZCR_ELx EndSysreg +Sysreg TRFCR_EL12 3 5 1 2 1 +Fields TRFCR_ELx +EndSysreg + Sysreg SMCR_EL12 3 5 1 2 6 Fields SMCR_ELx EndSysreg diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h index 345e81e0d2b3..150416682e2c 100644 --- a/tools/arch/arm64/include/asm/sysreg.h +++ b/tools/arch/arm64/include/asm/sysreg.h @@ -283,8 +283,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -519,7 +517,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) @@ -983,15 +980,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0)