From patchwork Wed Nov 13 21:11:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13874300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80A45D637C7 for ; Wed, 13 Nov 2024 21:17:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=8jWpUu0+gN6g2QC4B6zSiMqV9te+ZaKsIk2lVOXl6S0=; b=dIopvY8BDOKkR612qMFmMGXPvH MGAwL3Pe6OKcaL+GOHdPauzJp01x1seVjLr83NUbYUgaqsO7q1s3gnxl3dquJQlBF1N6NekrrRw+d tc7bb5eb1O3xoD/X5eg/lPnB3h9XVQmYBLmglATpgVBij+2QFUgz5E5dUWhix8bWfY7W1bM2jenDM wH7EbMjSGUkQ9rTnUp5xPpEOVYvinPdELKDyCeiGvkIGOhi17bl4Ed/me6YpZS9hFUDThbxpF2Ni0 Qg/kx0zbGF13qkN5Yp8JHn9tyI3lWoIslq7zpHJXkhcLdLzPNX0nKp7O0twoeGoD/qdrcl64kCtHF jlS0qyOw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBKjp-000000083MS-2gdg; Wed, 13 Nov 2024 21:17:21 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBKer-000000082Iq-0QcF for linux-arm-kernel@lists.infradead.org; Wed, 13 Nov 2024 21:12:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1731532333; x=1763068333; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=KeW3AYf2jpvtv6/CK8M/J7DhmMsyVE7KO7tfyVKcTQM=; b=MjT79KZ+E+PbasMLa/ZPgomC4zz++K5GhKSSnPN5BBEp8Qenswld30bF ztv6IOfzKbiWulleqZEUnYKoGUUDub/eD2mcezIMkR7LINmVaHNm1QC+E fhgbJfplhLspapz6eDi266/+a+H5V+jqOLFvcvkxQMosnhE6LQrJ8BzMQ eSxq0apQ00GmYRR/EldYZvp9KvX6Sf1oBYPlENGDhgN2bj1VMFXGWZwd+ NzQUBOdy2aZ82hKF8WXWK+RpIuEiMRyTYFmWifLz7wsxiz/M7UOv2dbEd tyFkqpHoiF0nuuYnajpedL3QW/5r0xZ09T2zGCz71VpJJZWibFGyi05Pw A==; X-CSE-ConnectionGUID: KA3skogJTWSLY1V4ky2YAQ== X-CSE-MsgGUID: SOa7Gp9mT5CFOabQAhTMcQ== X-IronPort-AV: E=Sophos;i="6.12,152,1728975600"; d="scan'208";a="265427893" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 13 Nov 2024 14:12:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 13 Nov 2024 14:11:37 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 13 Nov 2024 14:11:34 -0700 From: Daniel Machon Date: Wed, 13 Nov 2024 22:11:09 +0100 Subject: [PATCH net-next v2 1/8] net: sparx5: do some preparation work MIME-Version: 1.0 Message-ID: <20241113-sparx5-lan969x-switch-driver-4-v2-1-0db98ac096d1@microchip.com> References: <20241113-sparx5-lan969x-switch-driver-4-v2-0-0db98ac096d1@microchip.com> In-Reply-To: <20241113-sparx5-lan969x-switch-driver-4-v2-0-0db98ac096d1@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , , , , CC: , , , X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241113_131213_223312_A8AF9EEA X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The sparx5_port_init() does initial configuration of a variety of different features and options for each port. Some are shared for all types of devices, some are not. As it is now, common configuration is done after configuration of low-speed devices. This will not work when adding RGMII support in a subsequent patch. In preparation for lan969x RGMII support, move a block of code, that configures 2g5 devices, down. This ensures that the configuration common to all devices is done before configuration of 2g5, 5g, 10g and 25g devices. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/sparx5/sparx5_port.c | 36 +++++++++++----------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c index 1401761c6251..c929b2a63386 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -1067,24 +1067,6 @@ int sparx5_port_init(struct sparx5 *sparx5, if (err) return err; - /* Configure MAC vlan awareness */ - err = sparx5_port_max_tags_set(sparx5, port); - if (err) - return err; - - /* Set Max Length */ - spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), - DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, - sparx5, - DEV2G5_MAC_MAXLEN_CFG(port->portno)); - - /* 1G/2G5: Signal Detect configuration */ - spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | - DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | - DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), - sparx5, - DEV2G5_PCS1G_SD_CFG(port->portno)); - /* Set Pause WM hysteresis */ spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) | QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop) | @@ -1108,6 +1090,24 @@ int sparx5_port_init(struct sparx5 *sparx5, ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, sparx5, ANA_CL_FILTER_CTRL(port->portno)); + /* Configure MAC vlan awareness */ + err = sparx5_port_max_tags_set(sparx5, port); + if (err) + return err; + + /* Set Max Length */ + spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), + DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, + sparx5, + DEV2G5_MAC_MAXLEN_CFG(port->portno)); + + /* 1G/2G5: Signal Detect configuration */ + spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | + DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | + DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), + sparx5, + DEV2G5_PCS1G_SD_CFG(port->portno)); + if (conf->portmode == PHY_INTERFACE_MODE_QSGMII || conf->portmode == PHY_INTERFACE_MODE_SGMII) { err = sparx5_serdes_set(sparx5, port, conf);