From patchwork Sat Nov 16 18:22:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13877705 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3DD2D68BE7 for ; Sat, 16 Nov 2024 18:28:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uXLXOsSmzzJnI1euXZtIFU1GmJAoJ0qblGVgtPLX2Bs=; b=RNE1NeL+yt8iqZZBhU3HwAe8RQ TKMlD9svcpJyZk7X95BExAwL/gkalD47FZBGJmtmTo+/GWwg1cJmNQseIItxeUXn9qqRp7hT7cG7r 2YsSR9DGZwB2oQpi6/BN2ERcSgT1WWAyaloewgZKLzzpDZYVYdtuRNPyGcs543t0g55BT2NgaxiNT UFwKrVu1jbgc6LeCQw+hdYRvRFHyFfoWfd4fkcMtdMKTw2UJkW/TwBcwFwEZdVEO0icaFsV9GfXk7 raM5kI02h21pukLPDjpMeUD73/DXG7775PPehp97pkSWjlqtXAz81yHyixA5YUzwdwaV/UcPZzBoU bwraqpew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tCNWy-000000062t7-2BR0; Sat, 16 Nov 2024 18:28:24 +0000 Received: from bali.collaboradmins.com ([148.251.105.195]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tCNRa-000000061z8-3aoO; Sat, 16 Nov 2024 18:22:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1731781365; bh=uXHOo9+TzfRpI5IDnIvDAsLN/tG0WK21O4XtRokY5rA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HbcYmcuw3KJPwpeen8ioxtv0tN99gDIhC7+J248GqCRUeGsPLf7p0P4AlLJ6NSYoV LDLgkCJU8LE6MGVcKhpTYkLYR0K/GLDlWr7jrpI8mrzM33sOZCkIRyWYgKRlHcmQv9 b9r+vejMaaOTjzqjSkVFQPAC2TV9J3VsKiPGt5I+7DQTGG/55G/mtSYcq7bEYWPlCA 4dxtZf09hiVqQ+4UQUGa3t2jEzqSKOrQ3gdlJ0frXWs4YrA9wnJOndnFKdX6KM1Q/p m+9nUQYn1s9LzFgM+1AHuyZ+E4BrWgoON2gB1qVGvLa2IbA1ml+o9Smr87sgSt0BKY fndRSwruUh1HA== Received: from localhost (unknown [86.120.21.57]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9146917E377E; Sat, 16 Nov 2024 19:22:45 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 16 Nov 2024 20:22:36 +0200 Subject: [PATCH 5/5] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588 MIME-Version: 1.0 Message-Id: <20241116-vop2-hdmi0-disp-modes-v1-5-2bca51db4898@collabora.com> References: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> In-Reply-To: <20241116-vop2-hdmi0-disp-modes-v1-0-2bca51db4898@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241116_102251_096794_FF714C4E X-CRM114-Status: GOOD ( 10.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. For now only HDMI0 output is supported, hence add the related PLL clock. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 22462e86f48027ab7c5e270f2fa04df7afcc1d24..d07be2a81f28b4cbfe314992c662d8cfb3d3d344 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1262,14 +1262,16 @@ vop: vop@fdd90000 { <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy_hdmi0>; clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus = <&vop_mmu>; power-domains = <&power RK3588_PD_VOP>; rockchip,grf = <&sys_grf>;