@@ -18,6 +18,11 @@ properties:
- ti,am62-gpu
- const: img,img-axe-1-16m
- const: img,img-rogue
+ - items:
+ - enum:
+ - ti,j721s2-gpu
+ - const: img,img-bxs-4-64
+ - const: img,img-rogue
# This legacy combination of compatible strings was introduced early on before the more
# specific GPU identifiers were used. Keep it around here for compatibility, but never use
@@ -78,6 +83,18 @@ allOf:
properties:
power-domains:
maxItems: 1
+ # Cores with two power domains
+ - if:
+ properties:
+ compatible:
+ contains:
+ anyOf:
+ - const: img,img-bxs-4-64
+ then:
+ properties:
+ power-domains:
+ minItems: 2
+ maxItems: 2
# Vendor integrations using a single clock domain
- if:
properties:
@@ -85,6 +102,7 @@ allOf:
contains:
anyOf:
- const: ti,am62-gpu
+ - const: ti,j721s2-gpu
then:
properties:
clocks:
@@ -105,3 +123,26 @@ examples:
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
power-domain-names = "a";
};
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ / {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ gpu@4e20000000 {
+ compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue";
+ reg = <0x4e 0x20000000 0x00 0x80000>;
+ clocks = <&k3_clks 130 1>;
+ clock-names = "core";
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>;
+ power-domain-names = "a", "b";
+ dma-coherent;
+ };
+ };
Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock integration in the TI k3-j721s2. Signed-off-by: Matt Coster <matt.coster@imgtec.com> --- Changes in v2: - Use normal reg syntax for 64-bit values - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-8-4ed30e865892@imgtec.com --- .../devicetree/bindings/gpu/img,powervr-rogue.yaml | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+)