| Message ID | 20241119132916.1057797-2-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | RK3576 OTP support | expand |
On Tue Nov 19, 2024 at 2:29 PM CET, Heiko Stuebner wrote: > The phy clock of the OTP block is also present, but was not defined > so far. Though its clk-id already existed, so just define its location. > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > --- > drivers/clk/rockchip/clk-rk3576.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c > index 595e010341f7..029939a98416 100644 > --- a/drivers/clk/rockchip/clk-rk3576.c > +++ b/drivers/clk/rockchip/clk-rk3576.c > @@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { > RK3576_CLKGATE_CON(5), 14, GFLAGS), > GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, > RK3576_CLKGATE_CON(5), 15, GFLAGS), > + GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, > + RK3588_CLKGATE_CON(6), 0, GFLAGS), RK3588? Cheers, Diederik > COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0, > RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS, > RK3576_CLKGATE_CON(6), 3, GFLAGS),
Am Dienstag, 19. November 2024, 14:45:53 CET schrieb Diederik de Haas: > On Tue Nov 19, 2024 at 2:29 PM CET, Heiko Stuebner wrote: > > The phy clock of the OTP block is also present, but was not defined > > so far. Though its clk-id already existed, so just define its location. > > > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > --- > > drivers/clk/rockchip/clk-rk3576.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c > > index 595e010341f7..029939a98416 100644 > > --- a/drivers/clk/rockchip/clk-rk3576.c > > +++ b/drivers/clk/rockchip/clk-rk3576.c > > @@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { > > RK3576_CLKGATE_CON(5), 14, GFLAGS), > > GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, > > RK3576_CLKGATE_CON(5), 15, GFLAGS), > > + GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, > > + RK3588_CLKGATE_CON(6), 0, GFLAGS), > > RK3588? darn copy-paste, thanks for noticing ;-) At least the register and bit number is correct though ... according to the TRM. So I messed up only the constant and did not notice due to the gate being ungated by default of course. Heiko
diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c index 595e010341f7..029939a98416 100644 --- a/drivers/clk/rockchip/clk-rk3576.c +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { RK3576_CLKGATE_CON(5), 14, GFLAGS), GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, RK3576_CLKGATE_CON(5), 15, GFLAGS), + GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0, + RK3588_CLKGATE_CON(6), 0, GFLAGS), COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0, RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS, RK3576_CLKGATE_CON(6), 3, GFLAGS),
The phy clock of the OTP block is also present, but was not defined so far. Though its clk-id already existed, so just define its location. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- drivers/clk/rockchip/clk-rk3576.c | 2 ++ 1 file changed, 2 insertions(+)