From patchwork Thu Nov 21 09:23:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13881802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1CA6ED75BDF for ; Thu, 21 Nov 2024 09:26:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bXnii3hF6fRc2FqljrKIH3iXefjwAqibCeFB138aWZo=; b=yK0jPk0yc6+j83UqYr1eWONOer cjNNT6xhd9RqesF/PnMB8hgxcdOGeXSk6Jkzsl3j+/SrcBBzkOfHN7m/Tq6B0MPkLeIuhTPlKQbFY 7L9EhLMrBRn6Lcc5nIlbAcvEDz/vYb8h2OXKtpDzTrcSNM6GaCyShW+0tbtK9NIlQV+DGng3cS1/l pWV5Mlu3KDybrF23uKgyOEiZTgDMWbUnLpBOPrl4cD8tg8W0AfZ3hCwNqvTdGUHU9m5ZJktNLG6c2 EHOwzrrrXqiW5jOEzbUyEcL5q8/VvTstlxRjVfr0Ho1uwel/sLyuDLBdReZEBpDgVd+1v1DBYKuhz Y4xH5xAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tE3Ro-0000000HF6a-18oQ; Thu, 21 Nov 2024 09:26:00 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tE3Pc-0000000HEei-1XIY for linux-arm-kernel@lists.infradead.org; Thu, 21 Nov 2024 09:23:45 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1732181024; x=1763717024; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nxKf5QOaOvMz6pxHfw4grQb5c34JrR+fnuNyXv/1n9E=; b=purBsLWmkGzCJgSYR01/F4QmUSxjPiI+Shbhk5Tf8ssuNUJkrQDHO8BY uiflf+X8MfEX/6oEJSslQrwKaabF6F00WC7TzSn8TndW9uQ8JE3QwITXv 5zKD8m8/V+Qukl38YU6nc+X8GPF1rGFuejcgHLG4LeIEaso+06BibNbCH +0lCEsunQ53A65cDJBBS5qm3YuuCcKbbVU0wlMi+f7HwwsmFiNSqLwqpm Uu2G3Z9rXurX4eanyO8D7MLoJTFSfdfVe7+997jS1PeLFV7zPN2AoMRG6 GYIeC9X5Gf7HQkaeETph4aBJenSbmuZooPcPSdLeZeUpXuSFe8v7wxZRa g==; X-CSE-ConnectionGUID: wS72ZE3TTRmRyzdG8hxnTQ== X-CSE-MsgGUID: NcTGc9clQXmwz210lj1F0Q== X-IronPort-AV: E=Sophos;i="6.12,172,1728975600"; d="scan'208";a="202047029" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Nov 2024 02:23:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 21 Nov 2024 02:23:15 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 21 Nov 2024 02:23:11 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , CC: , Dharma Balasubiramani Subject: [PATCH 3/3] drm: atmel-hlcdc: set LVDS PLL clock rate for LVDS Displays Date: Thu, 21 Nov 2024 14:53:08 +0530 Message-ID: <20241121092308.130328-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241121092308.130328-1-manikandan.m@microchip.com> References: <20241121092308.130328-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241121_012344_464370_05D9C828 X-CRM114-Status: GOOD ( 14.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Dharma Balasubiramani The LVDS PLL clock is 7x the Panel Pixel clock. When using LVDS displays, the LVDS PLL clock rate is set using the panel pixel clock, this skips the usage of 'assigned-clock-rates' DT property for lvds_pll_clk clock for LCD node. Signed-off-by: Dharma Balasubiramani Signed-off-by: Manikandan Muralidharan --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 48 ++++++++++++++++--- 1 file changed, 42 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 0e709047369a..d11040d5cc5f 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -99,9 +99,15 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) drm_connector_list_iter_end(&iter); } - ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); - if (ret) - return; + if (crtc->dc->hlcdc->lvds_pll_clk) { + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + if (ret) + return; + } else { + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + if (ret) + return; + } vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end; @@ -186,7 +192,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), cfg); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); } static enum drm_mode_status @@ -242,7 +251,11 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, 10, 1000)) dev_warn(dev->dev, "Atmel LCDC status register CLKSTS timeout\n"); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + pinctrl_pm_select_sleep_state(dev->dev); pm_runtime_allow(dev->dev); @@ -255,15 +268,38 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct drm_display_mode *adj = &c->state->adjusted_mode; struct regmap *regmap = crtc->dc->hlcdc->regmap; unsigned int status; + int ret; pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); pinctrl_pm_select_default_state(dev->dev); - clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + + if (crtc->dc->hlcdc->lvds_pll_clk) { + /* + * When using LVDS displays, fetch the pixel clock from the panel + * and set the LVDS PLL clock rate. + * As per the datasheet, LVDS PLL clock is 7x the pixel clock. + */ + ret = clk_set_rate(crtc->dc->hlcdc->lvds_pll_clk, + (adj->clock * 7 * 1000)); + if (ret) { + dev_err(dev->dev, "Failed to set LVDS PLL clk rate: %d\n", ret); + return; + } + + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + if (ret) + return; + } else { + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + if (ret) + return; + } regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK); if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status,