Message ID | 20241125081814.397352-6-andrej.picej@norik.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | Update PHYTEC's i.MX8MM DTSs | expand |
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 7e859c65317a..cced82226c6d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -290,6 +290,7 @@ sn65dsi83: bridge@2d { status = "disabled"; }; + /* EEPROM */ eeprom@51 { compatible = "atmel,24c32"; pagesize = <32>; @@ -297,6 +298,7 @@ eeprom@51 { vcc-supply = <®_vdd_3v3_s>; }; + /* RTC */ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; @@ -307,7 +309,7 @@ rv3028: rtc@52 { }; }; -/* EMMC */ +/* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; assigned-clock-rates = <400000000>;