@@ -107,15 +107,15 @@
#define ID_AA64MMFR3_EL1_S2POE BITS(23, 20)
#define ID_AA64MMFR3_EL1_D128 BITS(35, 32)
+#define ID_AA64PFR0_EL1_RAS BITS(31, 28)
+#define ID_AA64PFR0_EL1_SVE BITS(35, 32)
+#define ID_AA64PFR0_EL1_CSV2 BITS(59, 56)
+
#define ID_AA64PFR1_EL1_MTE BITS(11, 8)
#define ID_AA64PFR1_EL1_SME BITS(27, 24)
#define ID_AA64PFR1_EL1_CSV2_frac BITS(35, 32)
#define ID_AA64PFR1_EL1_THE BITS(51, 48)
-#define ID_AA64PFR0_EL1_RAS BITS(31, 28)
-#define ID_AA64PFR0_EL1_SVE BITS(35, 32)
-#define ID_AA64PFR0_EL1_CSV2 BITS(59, 56)
-
#define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
#define ID_AA64SMFR0_EL1_FA64 BIT(63)
Usually the ID register definitions are sorted alphanumerically, but for historical reasons the ID_AA64PFR0_* definitions are placed before the ID_AA64PFR1_* definitions. Reorder these for consistency. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> --- arch/aarch64/include/asm/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)