Message ID | 20241205-upstream_s32cc_gmac-v8-1-ec1d180df815@oss.nxp.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | Add support for Synopsis DWMAC IP on NXP Automotive SoCs S32G2xx/S32G3xx/S32R45 | expand |
On Thu, Dec 05, 2024 at 05:42:58PM +0100, Jan Petrous via B4 Relay wrote: > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > The comment in declaration of STMMAC_CSR_250_300M > incorrectly describes the constant as '/* MDC = clk_scr_i/122 */' > but the DWC Ether QOS Handbook version 5.20a says it is > CSR clock/124. > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> > Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> I gave my reviewed-by for this patch in the previous posting, but you haven't included it. Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
On Thu, Dec 05, 2024 at 04:51:19PM +0000, Russell King (Oracle) wrote: > On Thu, Dec 05, 2024 at 05:42:58PM +0100, Jan Petrous via B4 Relay wrote: > > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > > > The comment in declaration of STMMAC_CSR_250_300M > > incorrectly describes the constant as '/* MDC = clk_scr_i/122 */' > > but the DWC Ether QOS Handbook version 5.20a says it is > > CSR clock/124. > > > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> > > Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> > > I gave my reviewed-by for this patch in the previous posting, but you > haven't included it. > > Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Hi Russell, sorry for that, I missed it. Should I resend the v8 series? BR. /Jan
On Thu, Dec 05, 2024 at 05:55:22PM +0100, Jan Petrous wrote: > On Thu, Dec 05, 2024 at 04:51:19PM +0000, Russell King (Oracle) wrote: > > On Thu, Dec 05, 2024 at 05:42:58PM +0100, Jan Petrous via B4 Relay wrote: > > > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > > > > > The comment in declaration of STMMAC_CSR_250_300M > > > incorrectly describes the constant as '/* MDC = clk_scr_i/122 */' > > > but the DWC Ether QOS Handbook version 5.20a says it is > > > CSR clock/124. > > > > > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> > > > Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> > > > > I gave my reviewed-by for this patch in the previous posting, but you > > haven't included it. > > > > Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> > > Hi Russell, > sorry for that, I missed it. Should I resend the v8 series? Patchwork will add it if this series is merged, so there's no immediate need to resend. However, please update your series with it in case there is another reason to send another version. Thanks.
On Thu, Dec 05, 2024 at 05:55:22PM +0100, Jan Petrous wrote: > On Thu, Dec 05, 2024 at 04:51:19PM +0000, Russell King (Oracle) wrote: > > On Thu, Dec 05, 2024 at 05:42:58PM +0100, Jan Petrous via B4 Relay wrote: > > > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > > > > > The comment in declaration of STMMAC_CSR_250_300M > > > incorrectly describes the constant as '/* MDC = clk_scr_i/122 */' > > > but the DWC Ether QOS Handbook version 5.20a says it is > > > CSR clock/124. > > > > > > Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> > > > Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> > > > > I gave my reviewed-by for this patch in the previous posting, but you > > haven't included it. > > > > Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> > > Hi Russell, > sorry for that, I missed it. Should I resend the v8 series? b4 is pretty good at handling this, it will find such tags and add them to your patchset if you are using b4 to manage it. Andrew
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index d79ff252cfdc..75cbfb576358 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -33,7 +33,7 @@ #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ -#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ +#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/124 */ /* MTL algorithms identifiers */ #define MTL_TX_ALGORITHM_WRR 0x0