| Message ID | 20241209085157.1203168-1-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: ti: k3-j784s4-j742s2-main-common: Enable ACSPCIE output for PCIe1 | expand |
On 14:21-20241209, Siddharth Vadapalli wrote: > The PCIe reference clock required by the PCIe Endpoints connected to the > PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM > and J742S2-EVM is driven by the ACSPCIE module. Add the device-tree support > for enabling the same. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > > Patch is based on linux-next tagged next-20241209. > > v1: > https://lore.kernel.org/r/20240715123301.1184833-1-s-vadapalli@ti.com/ > Changes since v1: > - Rebased patch on linux-next tagged next-20241209. > - Moved changes from "k3-j784s4-main.dtsi" to its equivalent now which > is "k3-j784s4-j742s2-main-common.dtsi" since PCIe1 is common to both > J742S2 and J784S4. > - Renamed "acspcie0-proxy-ctrl" to "clock-controller" to follow generic > node naming convention. > - Added "ti,syscon-acspcie-proxy-ctrl" property at the end of the node > since vendor specific properties should be placed at the end. > > Since all dependencies mentioned on the v1 patch have been merged, this > patch has no further dependencies. Patch has been tested on J784S4-EVM > with an NVMe SSD connected to the PCIe connector corresponding to PCIe1. > Logs: > https://gist.github.com/Siddharth-Vadapalli-at-TI/c36e30d8e9eb7bec96f7f400af1ea470 > > Regards, > Siddharth. > > .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > index 7721852c1f68..cddadd12f444 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi > @@ -7,6 +7,7 @@ > > #include <dt-bindings/mux/mux.h> > #include <dt-bindings/phy/phy.h> > +#include <dt-bindings/phy/phy-cadence.h> > #include <dt-bindings/phy/phy-ti.h> > > #include "k3-serdes.h" > @@ -124,6 +125,11 @@ audio_refclk1: clock@82e4 { > assigned-clock-parents = <&k3_clks 157 63>; > #clock-cells = <0>; > }; > + > + acspcie0_proxy_ctrl: clock-controller@1a090 { > + compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; I am on next-20241220 and dtbs_check throws this out, can you check? arch/arm64/boot/dts/ti/k3-am69-sk.dtb: clock-controller@1a090: compatible:0: 'ti,j784s4-acspcie-proxy-ctrl' is not one of ['al,alpine-sysfabric-service', 'allwinner,sun8i-a83t-system-controller', 'allwinner,sun8i-h3-system-controller', 'allwinner,sun8i-v3s-system-controller', 'allwinner,sun50i-a64-system-controller', 'altr,l3regs', 'altr,sdr-ctl', 'amd,pensando-elba-syscon', 'amlogic,meson-mx-assist', 'amlogic,meson-mx-bootrom', 'amlogic,meson8-analog-top', 'amlogic,meson8b-analog-top', 'amlogic,meson8-pmu', 'amlogic,meson8b-pmu', 'apm,merlin-poweroff-mailbox', 'apm,mustang-poweroff-mailbox', 'apm,xgene-csw', 'apm,xgene-efuse', 'apm,xgene-mcb', 'apm,xgene-rb', 'apm,xgene-scu', 'atmel,sama5d2-sfrbu', 'atmel,sama5d3-nfc-io', 'atmel,sama5d3-sfrbu', 'atmel,sama5d4-sfrbu', 'axis,artpec6-syscon', 'brcm,cru-clkset', 'brcm,sr-cdru', 'brcm,sr-mhb', 'cirrus,ep7209-syscon1', 'cirrus,ep7209-syscon2', 'cirrus,ep7209-syscon3', 'cnxt,cx92755-uc', 'freecom,fsg-cs2-system-controller', 'fsl,imx93-aonmix-ns-syscfg', 'fsl,imx93-wakeupmix-syscfg', 'fsl,ls1088a-reset', 'fsl,vf610-anatop', 'fsl,vf610-mscm-cpucfg', 'hisilicon,dsa-subctrl', 'hisilicon,hi6220-sramctrl', 'hisilicon,hip04-ppe', 'hisilicon,pcie-sas-subctrl', 'hisilicon,peri-subctrl', 'hpe,gxp-sysreg', 'loongson,ls1b-syscon', 'loongson,ls1c-syscon', 'lsi,axxia-syscon', 'marvell,armada-3700-cpu-misc', 'marvell,armada-3700-nb-pm', 'marvell,armada-3700-avs', 'marvell,armada-3700-usb2-host-misc', 'marvell,dove-global-config', 'mediatek,mt2701-pctl-a-syscfg', 'mediatek,mt2712-pctl-a-syscfg', 'mediatek,mt6397-pctl-pmic-syscfg', 'mediatek,mt8135-pctl-a-syscfg', 'mediatek,mt8135-pctl-b-syscfg', 'mediatek,mt8173-pctl-a-syscfg', 'mediatek,mt8365-syscfg', 'microchip,lan966x-cpu-syscon', 'microchip,mpfs-sysreg-scb', 'microchip,sam9x60-sfr', 'microchip,sama7g5-ddr3phy', 'mscc,ocelot-cpu-syscon', 'mstar,msc313-pmsleep', 'nuvoton,ma35d1-sys', 'nuvoton,wpcm450-shm', 'rockchip,px30-qos', 'rockchip,rk3036-qos', 'rockchip,rk3066-qos', 'rockchip,rk3128-qos', 'rockchip,rk3228-qos', 'rockchip,rk3288-qos', 'rockchip,rk3368-qos', 'rockchip,rk3399-qos', 'rockchip,rk3568-qos', 'rockchip,rk3576-qos', 'rockchip,rk3588-qos', 'rockchip,rv1126-qos', 'st,spear1340-misc', 'stericsson,nomadik-pmu', 'starfive,jh7100-sysmain', 'ti,am62-opp-efuse-table', 'ti,am62-usb-phy-ctrl', 'ti,am625-dss-oldi-io-ctrl', 'ti,am62p-cpsw-mac-efuse', 'ti,am654-dss-oldi-io-ctrl', 'ti,j784s4-pcie-ctrl', 'ti,keystone-pllctrl'] > + reg = <0x1a090 0x4>; > + }; > }; > > main_ehrpwm0: pwm@3000000 { > @@ -1091,8 +1097,8 @@ pcie1_rc: pcie@2910000 { > max-link-speed = <3>; > num-lanes = <4>; > power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; > - clocks = <&k3_clks 333 0>; > - clock-names = "fck"; > + clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; > + clock-names = "fck", "pcie_refclk"; > #address-cells = <3>; > #size-cells = <2>; > bus-range = <0x0 0xff>; > @@ -1103,6 +1109,7 @@ pcie1_rc: pcie@2910000 { > ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, > <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; > dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; > + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>; > status = "disabled"; > }; > > -- > 2.43.0 >
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 7721852c1f68..cddadd12f444 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/mux/mux.h> #include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy-ti.h> #include "k3-serdes.h" @@ -124,6 +125,11 @@ audio_refclk1: clock@82e4 { assigned-clock-parents = <&k3_clks 157 63>; #clock-cells = <0>; }; + + acspcie0_proxy_ctrl: clock-controller@1a090 { + compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon"; + reg = <0x1a090 0x4>; + }; }; main_ehrpwm0: pwm@3000000 { @@ -1091,8 +1097,8 @@ pcie1_rc: pcie@2910000 { max-link-speed = <3>; num-lanes = <4>; power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 333 0>; - clock-names = "fck"; + clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; #address-cells = <3>; #size-cells = <2>; bus-range = <0x0 0xff>; @@ -1103,6 +1109,7 @@ pcie1_rc: pcie@2910000 { ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>; status = "disabled"; };
The PCIe reference clock required by the PCIe Endpoints connected to the PCIe connector corresponding to the PCIe1 instance of PCIe on J784S4-EVM and J742S2-EVM is driven by the ACSPCIE module. Add the device-tree support for enabling the same. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- Patch is based on linux-next tagged next-20241209. v1: https://lore.kernel.org/r/20240715123301.1184833-1-s-vadapalli@ti.com/ Changes since v1: - Rebased patch on linux-next tagged next-20241209. - Moved changes from "k3-j784s4-main.dtsi" to its equivalent now which is "k3-j784s4-j742s2-main-common.dtsi" since PCIe1 is common to both J742S2 and J784S4. - Renamed "acspcie0-proxy-ctrl" to "clock-controller" to follow generic node naming convention. - Added "ti,syscon-acspcie-proxy-ctrl" property at the end of the node since vendor specific properties should be placed at the end. Since all dependencies mentioned on the v1 patch have been merged, this patch has no further dependencies. Patch has been tested on J784S4-EVM with an NVMe SSD connected to the PCIe connector corresponding to PCIe1. Logs: https://gist.github.com/Siddharth-Vadapalli-at-TI/c36e30d8e9eb7bec96f7f400af1ea470 Regards, Siddharth. .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)