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Lin" , Singo Chang , Nancy Lin , Moudy Ho , Xavier Chang , Subject: [PATCH v3 6/7] drm/mediatek: Add programming flow for unsupported subsys ID hardware Date: Fri, 20 Dec 2024 01:07:59 +0800 Message-ID: <20241219170800.2957-7-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241219170800.2957-1-jason-jh.lin@mediatek.com> References: <20241219170800.2957-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241219_091057_257626_42733093 X-CRM114-Status: GOOD ( 13.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support hardware without subsys IDs on new SoCs, add a programming flow that checks whether the subsys ID is valid. If the subsys ID is invalid, the flow will call 2 alternative CMDQ APIs: cmdq_pkt_assign() and cmdq_pkt_write_s_value() to achieve the same functionality. Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 33 ++++++++++++++++++++----- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index edc6417639e6..219d67735a54 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -66,14 +66,37 @@ struct mtk_ddp_comp_dev { struct cmdq_client_reg cmdq_reg; }; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +static void mtk_ddp_write_cmdq_pkt(struct cmdq_pkt *cmdq_pkt, struct cmdq_client_reg *cmdq_reg, + unsigned int offset, unsigned int value, unsigned int mask) +{ + offset += cmdq_reg->offset; + + if (cmdq_reg->subsys != CMDQ_SUBSYS_INVALID) { + if (mask == GENMASK(31, 0)) + cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, offset, value); + else + cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, offset, value, mask); + } else { + /* only MMIO access, no need to check mminfro_offset */ + cmdq_pkt_assign(cmdq_pkt, 0, CMDQ_ADDR_HIGH(cmdq_reg->pa_base)); + if (mask == GENMASK(31, 0)) + cmdq_pkt_write_s_value(cmdq_pkt, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_LOW(offset), value); + else + cmdq_pkt_write_s_mask_value(cmdq_pkt, CMDQ_THR_SPR_IDX0, + CMDQ_ADDR_LOW(offset), value, mask); + } +} +#endif + void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, struct cmdq_client_reg *cmdq_reg, void __iomem *regs, unsigned int offset) { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value); + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0)); else #endif writel(value, regs + offset); @@ -85,8 +108,7 @@ void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) - cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value); + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, GENMASK(31, 0)); else #endif writel_relaxed(value, regs + offset); @@ -98,8 +120,7 @@ void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, { #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (cmdq_pkt) { - cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, - cmdq_reg->offset + offset, value, mask); + mtk_ddp_write_cmdq_pkt(cmdq_pkt, cmdq_reg, offset, value, mask); } else { #endif u32 tmp = readl(regs + offset);