From patchwork Fri Dec 20 13:48:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13916795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 479D3E77188 for ; Fri, 20 Dec 2024 13:52:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References :Message-ID:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=udOoi6sPolCkEbA2sAStPHGWSr09KVGIkkP9UiJEge0=; b=r58bXB9PJFXW7TbEv1tEPn2WUB 0EzHEwBYSfzMBlbpLkFQkrs4CyKsOxR6IXLiGt0LcKvR7bQTDLP8gYWY+01H43YDarp5OwrXteYQK QkUgphQUjCBjgXT0B0IdXRSaB+iW2SASZW/yji2IIdDMKR95Ej8c4VIlobfyAvjCZuY+u4exZXyxK FLvQct0vEfb407Ui0LkKz9i2CwyLuVMGKuMCXb6YGAUyx0/FSGNgOM0TftFfbh51v5OnLsR5B1EiF NIxHLYQJLScYh2XymNdtwlD/3wSr/SE2etbHG5eZSGHe9izBnlOWr7ouSd3+qfLwmNxWVfuyv+n5Z DlZlRyKA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tOdQg-000000053bp-2G3i; Fri, 20 Dec 2024 13:52:34 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tOdNk-000000052yZ-122i for linux-arm-kernel@lists.infradead.org; Fri, 20 Dec 2024 13:49:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1734702572; x=1766238572; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Fa4MoYSUgEAXJYUJjfJyLnvfZej585cUVu/9qUSRj/4=; b=X3Q0/p4mVcius3CD611FsVcsl3cI3nNEQm1u4jEag/pJZLG3na/fv6sS qIBHB99HVb/6/QNzWdVHlLEmiOIZq35tMNy9o3vuaLyC5qMKZUUik/H7d 2YH+FFUaeWAbZ8JCR5hVx/GNG4T3XGv1LYnMIb7qF99H8rBHAza/UVIkJ GwYg5l4SBSlcsQAXKv2zoMuOECxgWStf7Dro/hM4acU0ehaSykx264XIC 8l+0puJzTn65uPIYZPtxnKvy+4vI3CBaqtANgHWz3wdkP+8WqSKxSFniK +c96Z1HXIXGnRQefQ8LFncSB4Do/I2Q72P/OoeRKI75RoT0rPoJchCs6k w==; X-CSE-ConnectionGUID: mIAoSPyhQLi+IAfuQfXUsw== X-CSE-MsgGUID: p1rymG+1Th2KUDbqhNuMNg== X-IronPort-AV: E=Sophos;i="6.12,250,1728975600"; d="scan'208";a="267028392" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Dec 2024 06:49:32 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 20 Dec 2024 06:48:54 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 20 Dec 2024 06:48:51 -0700 From: Daniel Machon Date: Fri, 20 Dec 2024 14:48:40 +0100 Subject: [PATCH net-next v5 1/9] net: sparx5: do some preparation work MIME-Version: 1.0 Message-ID: <20241220-sparx5-lan969x-switch-driver-4-v5-1-fa8ba5dff732@microchip.com> References: <20241220-sparx5-lan969x-switch-driver-4-v5-0-fa8ba5dff732@microchip.com> In-Reply-To: <20241220-sparx5-lan969x-switch-driver-4-v5-0-fa8ba5dff732@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , , , , CC: , , , , X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241220_054932_300334_6D88A65A X-CRM114-Status: GOOD ( 13.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The sparx5_port_init() does initial configuration of a variety of different features and options for each port. Some are shared for all types of devices, some are not. As it is now, common configuration is done after configuration of low-speed devices. This will not work when adding RGMII support in a subsequent patch. In preparation for lan969x RGMII support, move a block of code, that configures 2g5 devices, down. This ensures that the configuration common to all devices is done before configuration of 2g5, 5g, 10g and 25g devices. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Tested-by: Robert Marko Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/sparx5/sparx5_port.c | 36 +++++++++++----------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c index f9d1a6bb9bff..f39bf4878e11 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -1067,24 +1067,6 @@ int sparx5_port_init(struct sparx5 *sparx5, if (err) return err; - /* Configure MAC vlan awareness */ - err = sparx5_port_max_tags_set(sparx5, port); - if (err) - return err; - - /* Set Max Length */ - spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), - DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, - sparx5, - DEV2G5_MAC_MAXLEN_CFG(port->portno)); - - /* 1G/2G5: Signal Detect configuration */ - spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | - DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | - DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), - sparx5, - DEV2G5_PCS1G_SD_CFG(port->portno)); - /* Set Pause WM hysteresis */ spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) | QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop) | @@ -1108,6 +1090,24 @@ int sparx5_port_init(struct sparx5 *sparx5, ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, sparx5, ANA_CL_FILTER_CTRL(port->portno)); + /* Configure MAC vlan awareness */ + err = sparx5_port_max_tags_set(sparx5, port); + if (err) + return err; + + /* Set Max Length */ + spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), + DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, + sparx5, + DEV2G5_MAC_MAXLEN_CFG(port->portno)); + + /* 1G/2G5: Signal Detect configuration */ + spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | + DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | + DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), + sparx5, + DEV2G5_PCS1G_SD_CFG(port->portno)); + if (conf->portmode == PHY_INTERFACE_MODE_QSGMII || conf->portmode == PHY_INTERFACE_MODE_SGMII) { err = sparx5_serdes_set(sparx5, port, conf);