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[78.94.0.50]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-38a1c89e1a1sm4365193f8f.69.2024.12.20.08.32.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2024 08:32:49 -0800 (PST) From: Alicja Michalska To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alicja Michalska Subject: [PATCH] arm64: dts: rockchip: ROCK3B: Correct clock rates for Ethernet PHYs Date: Fri, 20 Dec 2024 17:32:27 +0100 Message-ID: <20241220163227.1501912-1-alicja.michalska@9elements.com> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241220_083252_272381_918EC62F X-CRM114-Status: GOOD ( 10.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Built-in ethernet PHYs did not work on mainline kernel: fe010000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0 fe010000.ethernet eth0: __stmmac_open: Cannot attach to PHY According to the board design, they need to be configured as output with static TX/RX delay. This patch sets it accordingly. Signed-off-by: Alicja Michalska --- .../boot/dts/rockchip/rk3568-rock-3b.dts | 68 +++++++++++-------- 1 file changed, 38 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts index 3d0c1ccfaa79..5350158302e4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -183,37 +183,65 @@ &cpu3 { &gmac0 { assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; - clock_in_out = "input"; - phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii-id"; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + phy-handle = <&rgmii_phy0>; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 &gmac0_rx_bus2 &gmac0_rgmii_clk - &gmac0_rgmii_bus - &gmac0_clkinout>; + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x36>; + rx_delay = <0x2d>; + status = "okay"; }; &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; - clock_in_out = "input"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-id"; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + phy-handle = <&rgmii_phy1>; pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus - &gmac1m1_clkinout>; + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 150000>; + + tx_delay = <0x47>; + rx_delay = <0x28>; + status = "okay"; }; +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &gpu { mali-supply = <&vdd_gpu>; status = "okay"; @@ -512,26 +540,6 @@ &i2s1m0_sdi0 status = "okay"; }; -&mdio0 { - rgmii_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - reset-assert-us = <20000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; - }; -}; - -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - reset-assert-us = <20000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; - }; -}; - &pcie2x1 { pinctrl-names = "default"; pinctrl-0 = <&pcie20m1_pins>;