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[2a02:3100:a5d7:4700::e63]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-aac0eae74e4sm658827166b.91.2024.12.24.06.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 06:30:37 -0800 (PST) From: Martin Blumenstingl To: linux-iio@vger.kernel.org, linux-amlogic@lists.infradead.org Cc: jic23@kernel.org, lars@metafoo.de, gnstark@salutedevices.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, neil.armstrong@linaro.org, Martin Blumenstingl Subject: [PATCH v2 2/3] iio: adc: meson: use tabs instead of spaces for some REG11 bit fields Date: Tue, 24 Dec 2024 15:29:40 +0100 Message-ID: <20241224142941.97759-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241224142941.97759-1-martin.blumenstingl@googlemail.com> References: <20241224142941.97759-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241224_063042_245641_444E9EF2 X-CRM114-Status: GOOD ( 10.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This makes them consistent with the rest of the driver. No functional changes. Signed-off-by: Martin Blumenstingl --- drivers/iio/adc/meson_saradc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 4cfbb3482a2e..469af3c57066 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -155,10 +155,10 @@ */ #define MESON_SAR_ADC_REG11 0x2c #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) - #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6) - #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5) - #define MESON_SAR_ADC_REG11_EOC BIT(1) - #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0) + #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6) + #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5) + #define MESON_SAR_ADC_REG11_EOC BIT(1) + #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0) #define MESON_SAR_ADC_REG13 0x34 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)