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Received: from [122.165.245.213] (port=50828 helo=[127.0.1.1]) by md-in-79.webhostbox.net with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1tR8Du-000bEK-0V; Fri, 27 Dec 2024 16:39:42 +0530 From: Parthiban Nallathambi Date: Fri, 27 Dec 2024 16:38:04 +0530 Subject: [PATCH 17/22] phy: allwinner: phy-sun6i-mipi-dphy: add LVDS support MIME-Version: 1.0 Message-Id: <20241227-a133-display-support-v1-17-13b52f71fb14@linumiz.com> References: <20241227-a133-display-support-v1-0-13b52f71fb14@linumiz.com> In-Reply-To: <20241227-a133-display-support-v1-0-13b52f71fb14@linumiz.com> To: Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter , Michael Turquette , Stephen Boyd , Philipp Zabel , Linus Walleij , Vinod Koul , Kishon Vijay Abraham I Cc: iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-phy@lists.infradead.org, Parthiban Nallathambi X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; 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Combo phy register have BIT(2) for enabling LVDS specifically, but enabling it alone isn't functional. Both MIPI and LVDS needs to be enabled in the combo phy to get the display working under LVDS mode. There is no specific enable bit for LVDS apart from the one in combo phy. MIPI got enable control in analog 4 register which must be disabled when using in LVDS mode. Introduce set_mode in phy ops to control only for MIPI DSI. Signed-off-by: Parthiban Nallathambi --- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c index 36eab95271b2..d164b2ea5dfd 100644 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c @@ -314,13 +314,11 @@ static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy) /* Disable sigma-delta modulation. */ regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0); - regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG, - SUN6I_DPHY_ANA4_REG_EN_MIPI, - SUN6I_DPHY_ANA4_REG_EN_MIPI); - regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0, + SUN50I_COMBO_PHY_REG0_EN_LVDS | SUN50I_COMBO_PHY_REG0_EN_MIPI | SUN50I_COMBO_PHY_REG0_EN_COMBOLDO, + SUN50I_COMBO_PHY_REG0_EN_LVDS | SUN50I_COMBO_PHY_REG0_EN_MIPI | SUN50I_COMBO_PHY_REG0_EN_COMBOLDO); @@ -528,6 +526,22 @@ static int sun6i_dphy_exit(struct phy *phy) return 0; } +static int sun6i_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct sun6i_dphy *dphy = phy_get_drvdata(phy); + + switch (mode) { + case PHY_MODE_MIPI_DPHY: + regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG, + SUN6I_DPHY_ANA4_REG_EN_MIPI, + SUN6I_DPHY_ANA4_REG_EN_MIPI); + break; + default: + return -EINVAL; + } + + return 0; +} static const struct phy_ops sun6i_dphy_ops = { .configure = sun6i_dphy_configure, @@ -535,6 +549,7 @@ static const struct phy_ops sun6i_dphy_ops = { .power_off = sun6i_dphy_power_off, .init = sun6i_dphy_init, .exit = sun6i_dphy_exit, + .set_mode = sun6i_set_mode, }; static const struct regmap_config sun6i_dphy_regmap_config = {