@@ -29,12 +29,12 @@ properties:
maxItems: 2
clocks:
- minItems: 6
- maxItems: 7
+ minItems: 7
+ maxItems: 10
clock-names:
- minItems: 6
- maxItems: 7
+ minItems: 7
+ maxItems: 10
'#clock-cells':
const: 1
@@ -94,6 +94,10 @@ allOf:
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
+ - description: audio1 PLL input
+ - description: audio2 PLL input
+ - description: dram PLL input
+ - description: video PLL input
clock-names:
items:
@@ -103,20 +107,31 @@ allOf:
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
+ - const: audio_pll1
+ - const: audio_pll2
+ - const: dram_pll
+ - const: video_pll
additionalProperties: false
examples:
# Clock Control Module node:
- |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+
clock-controller@30380000 {
compatible = "fsl,imx8mm-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
+ <&clk_ext3>, <&clk_ext4>,
+ <&anatop IMX8MM_ANATOP_AUDIO_PLL1>,
+ <&anatop IMX8MM_ANATOP_AUDIO_PLL1>,
+ <&anatop IMX8MM_ANATOP_DRAM_PLL>,
+ <&anatop IMX8MM_ANATOP_VIDEO_PLL>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
+ "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2",
+ "dram_pll", "video_pll";
fsl,anatop = <&anatop>;
};