From patchwork Tue Dec 31 06:00:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jian Hu X-Patchwork-Id: 13923635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9FBC3E77188 for ; Tue, 31 Dec 2024 06:04:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tALuKTQsLwbpMjpMjiG52NclZUbvYTMTTObuW17EOAk=; b=eOlDUElLCb+Yfx4bk/ZTq++Gy1 OvfG15vyf8avpqH60G3aJdBZgF+SjJGS4DCVCTQ8ZkicYQAcbkC7OyCVSzl7yOvHxK52g7Svs5wU0 tmbU57D5/vLFU+qMHTT1e7hmID+XUFYXmOl9fCiwW62faU/RlfGwvq8fUBv+7xX6iRAOvQCsMMvx3 v4A2X43GXs063fcaQIWoB+oVhSodafeNGWVuWI2c6GGoT0cL2z/c+uSPdyhDkQummY8Lbd7KSR8fD NHZWQfTvYwzOzWlPeU7bwdT+2/k7AV1gdJ/8nXzScRxwdYbo9qgWR6p4Js70Mr+vPRe8ZBFacB+B1 eQYnoGhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tSVMs-00000006bQW-0pQT; Tue, 31 Dec 2024 06:04:38 +0000 Received: from [58.32.228.46] (helo=mail-sh.amlogic.com) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tSVJV-00000006aoV-1rLL; Tue, 31 Dec 2024 06:01:10 +0000 Received: from rd03-sz.software.amlogic (10.28.11.121) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.39; Tue, 31 Dec 2024 14:00:51 +0800 From: Jian Hu To: Jerome Brunet , Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , "Stephen Boyd" , Michael Turquette , "Dmitry Rokosov" , robh+dt , Rob Herring CC: Jian Hu , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel Subject: [PATCH 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller Date: Tue, 31 Dec 2024 14:00:44 +0800 Message-ID: <20241231060047.2298871-3-jian.hu@amlogic.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241231060047.2298871-1-jian.hu@amlogic.com> References: <20241231060047.2298871-1-jian.hu@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.11.121] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241230_220109_478864_6FE3FCB1 X-CRM114-Status: UNSURE ( 9.90 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu Acked-by: Rob Herring (Arm) --- include/dt-bindings/clock/amlogic,t7-scmi.h | 48 +++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h diff --git a/include/dt-bindings/clock/amlogic,t7-scmi.h b/include/dt-bindings/clock/amlogic,t7-scmi.h new file mode 100644 index 000000000000..aa2431ea72ed --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-scmi.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + */ + +#ifndef __T7_SCMI_CLKC_H +#define __T7_SCMI_CLKC_H + +#define CLKID_DDR_PLL_OSC 0 +#define CLKID_AUD_PLL_OSC 1 +#define CLKID_TOP_PLL_OSC 2 +#define CLKID_TCON_PLL_OSC 3 +#define CLKID_USB_PLL0_OSC 4 +#define CLKID_USB_PLL1_OSC 5 +#define CLKID_MCLK_PLL_OSC 6 +#define CLKID_PCIE_OSC 7 +#define CLKID_ETH_PLL_OSC 8 +#define CLKID_PCIE_REFCLK_PLL_OSC 9 +#define CLKID_EARC_OSC 10 +#define CLKID_SYS1_PLL_OSC 11 +#define CLKID_HDMI_PLL_OSC 12 +#define CLKID_SYS_CLK 13 +#define CLKID_AXI_CLK 14 +#define CLKID_FIXED_PLL_DCO 15 +#define CLKID_FIXED_PLL 16 +#define CLKID_FCLK_DIV2_DIV 17 +#define CLKID_FCLK_DIV2 18 +#define CLKID_FCLK_DIV2P5_DIV 19 +#define CLKID_FCLK_DIV2P5 20 +#define CLKID_FCLK_DIV3_DIV 21 +#define CLKID_FCLK_DIV3 22 +#define CLKID_FCLK_DIV4_DIV 23 +#define CLKID_FCLK_DIV4 24 +#define CLKID_FCLK_DIV5_DIV 25 +#define CLKID_FCLK_DIV5 26 +#define CLKID_FCLK_DIV7_DIV 27 +#define CLKID_FCLK_DIV7 28 +#define CLKID_FCLK_50M_DIV 29 +#define CLKID_FCLK_50M 30 +#define CLKID_CPU_CLK 31 +#define CLKID_A73_CLK 32 +#define CLKID_CPU_CLK_DIV16_DIV 33 +#define CLKID_CPU_CLK_DIV16 34 +#define CLKID_A73_CLK_DIV16_DIV 35 +#define CLKID_A73_CLK_DIV16 36 + +#endif /* __T7_SCMI_CLKC_H */